1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Configuation settings for the Freescale MCF52277 EVB board. 4 * 5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 */ 8 9 /* 10 * board/config.h - configuration options, board specific 11 */ 12 13 #ifndef _M52277EVB_H 14 #define _M52277EVB_H 15 16 #include <linux/stringify.h> 17 18 /* 19 * High Level Configuration Options 20 * (easy to change) 21 */ 22 23 #define CONFIG_MCFUART 24 #define CONFIG_SYS_UART_PORT (0) 25 26 #undef CONFIG_WATCHDOG 27 28 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 29 30 /* 31 * BOOTP options 32 */ 33 #define CONFIG_BOOTP_BOOTFILESIZE 34 35 #define CONFIG_HOSTNAME "M52277EVB" 36 #define CONFIG_SYS_UBOOT_END 0x3FFFF 37 #define CONFIG_SYS_LOAD_ADDR2 0x40010007 38 #ifdef CONFIG_SYS_STMICRO_BOOT 39 /* ST Micro serial flash */ 40 #define CONFIG_EXTRA_ENV_SETTINGS \ 41 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 42 "loadaddr=0x40010000\0" \ 43 "uboot=u-boot.bin\0" \ 44 "load=loadb ${loadaddr} ${baudrate};" \ 45 "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ 46 "upd=run load; run prog\0" \ 47 "prog=sf probe 0:2 10000 1;" \ 48 "sf erase 0 30000;" \ 49 "sf write ${loadaddr} 0 30000;" \ 50 "save\0" \ 51 "" 52 #endif 53 #ifdef CONFIG_SYS_SPANSION_BOOT 54 #define CONFIG_EXTRA_ENV_SETTINGS \ 55 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 56 "loadaddr=0x40010000\0" \ 57 "uboot=u-boot.bin\0" \ 58 "load=loadb ${loadaddr} ${baudrate}\0" \ 59 "upd=run load; run prog\0" \ 60 "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \ 61 " " __stringify(CONFIG_SYS_UBOOT_END) ";" \ 62 "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \ 63 __stringify(CONFIG_SYS_UBOOT_END) ";" \ 64 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \ 65 " ${filesize}; save\0" \ 66 "updsbf=run loadsbf; run progsbf\0" \ 67 "loadsbf=loadb ${loadaddr} ${baudrate};" \ 68 "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ 69 "progsbf=sf probe 0:2 10000 1;" \ 70 "sf erase 0 30000;" \ 71 "sf write ${loadaddr} 0 30000;" \ 72 "" 73 #endif 74 75 /* LCD */ 76 #ifdef CONFIG_CMD_BMP 77 #define CONFIG_LCD_LOGO 78 #define CONFIG_SHARP_LQ035Q7DH06 79 #endif 80 81 /* USB */ 82 #ifdef CONFIG_CMD_USB 83 #define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000 84 #define CONFIG_SYS_USB_EHCI_CPU_INIT 85 #endif 86 87 /* Realtime clock */ 88 #define CONFIG_MCFRTC 89 #undef RTC_DEBUG 90 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) 91 92 /* Timer */ 93 #define CONFIG_MCFTMR 94 95 /* I2c */ 96 #define CONFIG_SYS_I2C 97 #define CONFIG_SYS_I2C_FSL 98 #define CONFIG_SYS_FSL_I2C_SPEED 80000 99 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 100 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 101 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 102 103 /* DSPI and Serial Flash */ 104 #define CONFIG_CF_DSPI 105 #define CONFIG_SYS_SBFHDR_SIZE 0x7 106 107 /* Input, PCI, Flexbus, and VCO */ 108 #define CONFIG_EXTRA_CLOCK 109 110 #define CONFIG_SYS_INPUT_CLKSRC 16000000 111 112 #define CONFIG_PRAM 2048 /* 2048 KB */ 113 114 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 115 116 #define CONFIG_SYS_MBAR 0xFC000000 117 118 /* 119 * Low Level Configuration Settings 120 * (address mappings, register initial values, etc.) 121 * You should know what you are doing if you make changes here. 122 */ 123 124 /* 125 * Definitions for initial stack pointer and data area (in DPRAM) 126 */ 127 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 128 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 129 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 130 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) 131 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32) 132 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 133 134 /* 135 * Start addresses for the final memory configuration 136 * (Set up by the startup code) 137 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 138 */ 139 #define CONFIG_SYS_SDRAM_BASE 0x40000000 140 #define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ 141 #define CONFIG_SYS_SDRAM_CFG1 0x43711630 142 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 143 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 144 #define CONFIG_SYS_SDRAM_EMOD 0x81810000 145 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 146 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x00 147 148 #ifdef CONFIG_CF_SBF 149 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 150 #else 151 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 152 #endif 153 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 154 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 155 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 156 157 /* Initial Memory map for Linux */ 158 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 159 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 160 161 /* 162 * Configuration for environment 163 * Environment is not embedded in u-boot. First time runing may have env 164 * crc error warning if there is no correct environment on the flash. 165 */ 166 167 /*----------------------------------------------------------------------- 168 * FLASH organization 169 */ 170 #ifdef CONFIG_SYS_STMICRO_BOOT 171 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 172 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 173 #endif 174 #ifdef CONFIG_SYS_SPANSION_BOOT 175 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 176 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 177 #endif 178 179 #ifdef CONFIG_SYS_FLASH_CFI 180 # define CONFIG_FLASH_SPANSION_S29WS_N 1 181 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 182 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 183 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 184 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 185 # define CONFIG_SYS_FLASH_CHECKSUM 186 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } 187 #endif 188 189 #define LDS_BOARD_TEXT \ 190 arch/m68k/cpu/mcf5227x/built-in.o (.text*) \ 191 arch/m68k/lib/built-in.o (.text*) 192 193 /* 194 * This is setting for JFFS2 support in u-boot. 195 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 196 */ 197 #ifdef CONFIG_CMD_JFFS2 198 # define CONFIG_JFFS2_DEV "nor0" 199 # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x40000) 200 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x40000) 201 #endif 202 203 /*----------------------------------------------------------------------- 204 * Cache Configuration 205 */ 206 #define CONFIG_SYS_CACHELINE_SIZE 16 207 208 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 209 CONFIG_SYS_INIT_RAM_SIZE - 8) 210 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 211 CONFIG_SYS_INIT_RAM_SIZE - 4) 212 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) 213 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 214 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 215 CF_ACR_EN | CF_ACR_SM_ALL) 216 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ 217 CF_CACR_DISD | CF_CACR_INVI | \ 218 CF_CACR_CEIB | CF_CACR_DCM | \ 219 CF_CACR_EUSP) 220 221 /*----------------------------------------------------------------------- 222 * Memory bank definitions 223 */ 224 /* 225 * CS0 - NOR Flash 226 * CS1 - Available 227 * CS2 - Available 228 * CS3 - Available 229 * CS4 - Available 230 * CS5 - Available 231 */ 232 233 #ifdef CONFIG_CF_SBF 234 #define CONFIG_SYS_CS0_BASE 0x04000000 235 #define CONFIG_SYS_CS0_MASK 0x00FF0001 236 #define CONFIG_SYS_CS0_CTRL 0x00001FA0 237 #else 238 #define CONFIG_SYS_CS0_BASE 0x00000000 239 #define CONFIG_SYS_CS0_MASK 0x00FF0001 240 #define CONFIG_SYS_CS0_CTRL 0x00001FA0 241 #endif 242 243 #endif /* _M52277EVB_H */ 244