1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Configuation settings for the Motorola MC5275EVB board. 4 * 5 * By Arthur Shipkowski <art@videon-central.com> 6 * Copyright (C) 2005 Videon Central, Inc. 7 * 8 * Based off of M5272C3 board code by Josef Baumgartner 9 * <josef.baumgartner@telex.de> 10 */ 11 12 /* 13 * board/config.h - configuration options, board specific 14 */ 15 16 #ifndef _M5275EVB_H 17 #define _M5275EVB_H 18 19 /* 20 * High Level Configuration Options 21 * (easy to change) 22 */ 23 24 #define CONFIG_MCFTMR 25 26 #define CONFIG_MCFUART 27 #define CONFIG_SYS_UART_PORT (0) 28 29 /* Configuration for environment 30 * Environment is embedded in u-boot in the second sector of the flash 31 */ 32 33 #define LDS_BOARD_TEXT \ 34 . = DEFINED(env_offset) ? env_offset : .; \ 35 env/embedded.o(.text); 36 37 /* 38 * BOOTP options 39 */ 40 #define CONFIG_BOOTP_BOOTFILESIZE 41 42 /* Available command configuration */ 43 44 #ifdef CONFIG_MCFFEC 45 #define CONFIG_MII_INIT 1 46 #define CONFIG_SYS_DISCOVER_PHY 47 #define CONFIG_SYS_RX_ETH_BUFFER 8 48 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 49 #define CONFIG_HAS_ETH1 50 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 51 #ifndef CONFIG_SYS_DISCOVER_PHY 52 #define FECDUPLEX FULL 53 #define FECSPEED _100BASET 54 #else 55 #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 56 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 57 #endif 58 #endif 59 #endif 60 61 /* I2C */ 62 #define CONFIG_SYS_I2C 63 #define CONFIG_SYS_I2C_FSL 64 #define CONFIG_SYS_FSL_I2C_SPEED 80000 65 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 66 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 67 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 68 #define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c) 69 #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0) 70 #define CONFIG_SYS_I2C_PINMUX_SET (0x000F) 71 72 #define CONFIG_SYS_LOAD_ADDR 0x800000 73 74 #define CONFIG_BOOTCOMMAND "bootm ffe40000" 75 76 #ifdef CONFIG_MCFFEC 77 # define CONFIG_NET_RETRY_COUNT 5 78 # define CONFIG_OVERWRITE_ETHADDR_ONCE 79 #endif /* FEC_ENET */ 80 81 #define CONFIG_EXTRA_ENV_SETTINGS \ 82 "netdev=eth0\0" \ 83 "loadaddr=10000\0" \ 84 "uboot=u-boot.bin\0" \ 85 "load=tftp ${loadaddr} ${uboot}\0" \ 86 "upd=run load; run prog\0" \ 87 "prog=prot off ffe00000 ffe3ffff;" \ 88 "era ffe00000 ffe3ffff;" \ 89 "cp.b ${loadaddr} ffe00000 ${filesize};"\ 90 "save\0" \ 91 "" 92 93 #define CONFIG_SYS_CLK 150000000 94 95 /* 96 * Low Level Configuration Settings 97 * (address mappings, register initial values, etc.) 98 * You should know what you are doing if you make changes here. 99 */ 100 101 #define CONFIG_SYS_MBAR 0x40000000 102 103 /*----------------------------------------------------------------------- 104 * Definitions for initial stack pointer and data area (in DPRAM) 105 */ 106 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 107 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 108 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 109 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 110 111 /*----------------------------------------------------------------------- 112 * Start addresses for the final memory configuration 113 * (Set up by the startup code) 114 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 115 */ 116 #define CONFIG_SYS_SDRAM_BASE 0x00000000 117 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 118 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 119 120 #ifdef CONFIG_MONITOR_IS_IN_RAM 121 #define CONFIG_SYS_MONITOR_BASE 0x20000 122 #else 123 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 124 #endif 125 126 #define CONFIG_SYS_MONITOR_LEN 0x20000 127 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 128 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 129 130 /* 131 * For booting Linux, the board info and command line data 132 * have to be in the first 8 MB of memory, since this is 133 * the maximum mapped by the Linux kernel during initialization ?? 134 */ 135 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 136 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 137 138 /*----------------------------------------------------------------------- 139 * FLASH organization 140 */ 141 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 142 #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ 143 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 144 145 #define CONFIG_SYS_FLASH_SIZE 0x200000 146 147 /*----------------------------------------------------------------------- 148 * Cache Configuration 149 */ 150 #define CONFIG_SYS_CACHELINE_SIZE 16 151 152 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 153 CONFIG_SYS_INIT_RAM_SIZE - 8) 154 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 155 CONFIG_SYS_INIT_RAM_SIZE - 4) 156 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) 157 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 158 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 159 CF_ACR_EN | CF_ACR_SM_ALL) 160 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ 161 CF_CACR_DISD | CF_CACR_INVI | \ 162 CF_CACR_CEIB | CF_CACR_DCM | \ 163 CF_CACR_EUSP) 164 165 /*----------------------------------------------------------------------- 166 * Memory bank definitions 167 */ 168 #define CONFIG_SYS_CS0_BASE 0xffe00000 169 #define CONFIG_SYS_CS0_CTRL 0x00001980 170 #define CONFIG_SYS_CS0_MASK 0x001F0001 171 172 #define CONFIG_SYS_CS1_BASE 0x30000000 173 #define CONFIG_SYS_CS1_CTRL 0x00001900 174 #define CONFIG_SYS_CS1_MASK 0x00070001 175 176 /*----------------------------------------------------------------------- 177 * Port configuration 178 */ 179 #define CONFIG_SYS_FECI2C 0x0FA0 180 181 #endif /* _M5275EVB_H */ 182