1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2006-2010 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 */ 6 7 /* 8 * mpc8349emds board configuration file 9 * 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 /* 16 * High Level Configuration Options 17 */ 18 #define CONFIG_E300 1 /* E300 Family */ 19 20 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 21 22 /* 23 * DDR Setup 24 */ 25 #define CONFIG_DDR_ECC /* support DDR ECC function */ 26 #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 27 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 28 29 /* 30 * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver 31 * unselect it to use old spd_sdram.c 32 */ 33 #define CONFIG_SYS_SPD_BUS_NUM 0 34 #define SPD_EEPROM_ADDRESS1 0x52 35 #define SPD_EEPROM_ADDRESS2 0x51 36 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 37 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 38 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 39 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 40 41 /* 42 * 32-bit data path mode. 43 * 44 * Please note that using this mode for devices with the real density of 64-bit 45 * effectively reduces the amount of available memory due to the effect of 46 * wrapping around while translating address to row/columns, for example in the 47 * 256MB module the upper 128MB get aliased with contents of the lower 48 * 128MB); normally this define should be used for devices with real 32-bit 49 * data path. 50 */ 51 #undef CONFIG_DDR_32BIT 52 53 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 54 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ 55 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 56 #undef CONFIG_DDR_2T_TIMING 57 58 /* 59 * DDRCDR - DDR Control Driver Register 60 */ 61 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001 62 63 #if defined(CONFIG_SPD_EEPROM) 64 /* 65 * Determine DDR configuration from I2C interface. 66 */ 67 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 68 #else 69 /* 70 * Manually set up DDR parameters 71 */ 72 #define CONFIG_SYS_DDR_SIZE 256 /* MB */ 73 #if defined(CONFIG_DDR_II) 74 #define CONFIG_SYS_DDRCDR 0x80080001 75 #define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f 76 #define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102 77 #define CONFIG_SYS_DDR_TIMING_0 0x00220802 78 #define CONFIG_SYS_DDR_TIMING_1 0x38357322 79 #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 80 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 81 #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 82 #define CONFIG_SYS_DDR_MODE 0x47d00432 83 #define CONFIG_SYS_DDR_MODE2 0x8000c000 84 #define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 85 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 86 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 87 #else 88 #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ 89 | CSCONFIG_ROW_BIT_13 \ 90 | CSCONFIG_COL_BIT_10) 91 #define CONFIG_SYS_DDR_TIMING_1 0x36332321 92 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 93 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 94 #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ 95 96 #if defined(CONFIG_DDR_32BIT) 97 /* set burst length to 8 for 32-bit data path */ 98 /* DLL,normal,seq,4/2.5, 8 burst len */ 99 #define CONFIG_SYS_DDR_MODE 0x00000023 100 #else 101 /* the default burst length is 4 - for 64-bit data path */ 102 /* DLL,normal,seq,4/2.5, 4 burst len */ 103 #define CONFIG_SYS_DDR_MODE 0x00000022 104 #endif 105 #endif 106 #endif 107 108 /* 109 * SDRAM on the Local Bus 110 */ 111 #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ 112 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 113 114 /* 115 * FLASH on the Local Bus 116 */ 117 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 118 #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ 119 120 121 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 122 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ 123 124 #undef CONFIG_SYS_FLASH_CHECKSUM 125 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 126 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 127 128 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 129 130 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 131 #define CONFIG_SYS_RAMBOOT 132 #else 133 #undef CONFIG_SYS_RAMBOOT 134 #endif 135 136 /* 137 * BCSR register on local bus 32KB, 8-bit wide for MDS config reg 138 */ 139 #define CONFIG_SYS_BCSR 0xE2400000 140 /* Access window base at BCSR base */ 141 142 143 #define CONFIG_SYS_INIT_RAM_LOCK 1 144 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 145 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 146 147 #define CONFIG_SYS_GBL_DATA_OFFSET \ 148 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 149 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 150 151 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 152 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ 153 154 /* 155 * Serial Port 156 */ 157 #define CONFIG_SYS_NS16550_SERIAL 158 #define CONFIG_SYS_NS16550_REG_SIZE 1 159 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 160 161 #define CONFIG_SYS_BAUDRATE_TABLE \ 162 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 163 164 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 165 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 166 167 /* I2C */ 168 #define CONFIG_SYS_I2C 169 #define CONFIG_SYS_I2C_FSL 170 #define CONFIG_SYS_FSL_I2C_SPEED 400000 171 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 172 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 173 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 174 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 175 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 176 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 177 178 /* SPI */ 179 #undef CONFIG_SOFT_SPI /* SPI bit-banged */ 180 181 /* GPIOs. Used as SPI chip selects */ 182 #define CONFIG_SYS_GPIO1_PRELIM 183 #define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */ 184 #define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */ 185 186 /* TSEC */ 187 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 188 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 189 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 190 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 191 192 /* USB */ 193 #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ 194 195 /* 196 * General PCI 197 * Addresses are mapped 1-1. 198 */ 199 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 200 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 201 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 202 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 203 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 204 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 205 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 206 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 207 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 208 209 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 210 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 211 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 212 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 213 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 214 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 215 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 216 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 217 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 218 219 #if defined(CONFIG_PCI) 220 221 #define CONFIG_83XX_PCI_STREAMING 222 223 224 #if !defined(CONFIG_PCI_PNP) 225 #define PCI_ENET0_IOADDR 0xFIXME 226 #define PCI_ENET0_MEMADDR 0xFIXME 227 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 228 #endif 229 230 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 231 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 232 233 #endif /* CONFIG_PCI */ 234 235 /* 236 * TSEC configuration 237 */ 238 239 #if defined(CONFIG_TSEC_ENET) 240 241 #define CONFIG_GMII 1 /* MII PHY management */ 242 #define CONFIG_TSEC1 1 243 #define CONFIG_TSEC1_NAME "TSEC0" 244 #define CONFIG_TSEC2 1 245 #define CONFIG_TSEC2_NAME "TSEC1" 246 #define TSEC1_PHY_ADDR 0 247 #define TSEC2_PHY_ADDR 1 248 #define TSEC1_PHYIDX 0 249 #define TSEC2_PHYIDX 0 250 #define TSEC1_FLAGS TSEC_GIGABIT 251 #define TSEC2_FLAGS TSEC_GIGABIT 252 253 /* Options are: TSEC[0-1] */ 254 #define CONFIG_ETHPRIME "TSEC0" 255 256 #endif /* CONFIG_TSEC_ENET */ 257 258 /* 259 * Configure on-board RTC 260 */ 261 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 262 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 263 264 /* 265 * Environment 266 */ 267 #ifndef CONFIG_SYS_RAMBOOT 268 /* Address and size of Redundant Environment Sector */ 269 #endif 270 271 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 272 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 273 274 /* 275 * BOOTP options 276 */ 277 #define CONFIG_BOOTP_BOOTFILESIZE 278 279 #undef CONFIG_WATCHDOG /* watchdog disabled */ 280 281 /* 282 * Miscellaneous configurable options 283 */ 284 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 285 286 /* 287 * For booting Linux, the board info and command line data 288 * have to be in the first 256 MB of memory, since this is 289 * the maximum mapped by the Linux kernel during initialization. 290 */ 291 /* Initial Memory map for Linux*/ 292 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 293 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 294 295 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 296 297 /* 298 * System performance 299 */ 300 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ 301 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ 302 303 /* System IO Config */ 304 #define CONFIG_SYS_SICRH 0 305 #define CONFIG_SYS_SICRL SICRL_LDP_A 306 307 #ifdef CONFIG_PCI 308 #define CONFIG_PCI_INDIRECT_BRIDGE 309 #endif 310 311 #if defined(CONFIG_CMD_KGDB) 312 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 313 #endif 314 315 /* 316 * Environment Configuration 317 */ 318 319 #if defined(CONFIG_TSEC_ENET) 320 #define CONFIG_HAS_ETH1 321 #define CONFIG_HAS_ETH0 322 #endif 323 324 #define CONFIG_HOSTNAME "mpc8349emds" 325 #define CONFIG_ROOTPATH "/nfsroot/rootfs" 326 #define CONFIG_BOOTFILE "uImage" 327 328 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 329 330 #define CONFIG_EXTRA_ENV_SETTINGS \ 331 "netdev=eth0\0" \ 332 "hostname=mpc8349emds\0" \ 333 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 334 "nfsroot=${serverip}:${rootpath}\0" \ 335 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 336 "addip=setenv bootargs ${bootargs} " \ 337 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 338 ":${hostname}:${netdev}:off panic=1\0" \ 339 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 340 "flash_nfs=run nfsargs addip addtty;" \ 341 "bootm ${kernel_addr}\0" \ 342 "flash_self=run ramargs addip addtty;" \ 343 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 344 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 345 "bootm\0" \ 346 "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ 347 "update=protect off fe000000 fe03ffff; " \ 348 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\ 349 "upd=run load update\0" \ 350 "fdtaddr=780000\0" \ 351 "fdtfile=mpc834x_mds.dtb\0" \ 352 "" 353 354 #define CONFIG_NFSBOOTCOMMAND \ 355 "setenv bootargs root=/dev/nfs rw " \ 356 "nfsroot=$serverip:$rootpath " \ 357 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 358 "$netdev:off " \ 359 "console=$consoledev,$baudrate $othbootargs;" \ 360 "tftp $loadaddr $bootfile;" \ 361 "tftp $fdtaddr $fdtfile;" \ 362 "bootm $loadaddr - $fdtaddr" 363 364 #define CONFIG_RAMBOOTCOMMAND \ 365 "setenv bootargs root=/dev/ram rw " \ 366 "console=$consoledev,$baudrate $othbootargs;" \ 367 "tftp $ramdiskaddr $ramdiskfile;" \ 368 "tftp $loadaddr $bootfile;" \ 369 "tftp $fdtaddr $fdtfile;" \ 370 "bootm $loadaddr $ramdiskaddr $fdtaddr" 371 372 #define CONFIG_BOOTCOMMAND "run flash_self" 373 374 #endif /* __CONFIG_H */ 375