1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2004, 2011 Freescale Semiconductor. 4 */ 5 6 /* 7 * mpc8541cds board configuration file 8 * 9 * Please refer to doc/README.mpc85xxcds for more info. 10 * 11 */ 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 /* High Level Configuration Options */ 16 #define CONFIG_CPM2 1 /* has CPM2 */ 17 18 #define CONFIG_PCI_INDIRECT_BRIDGE 19 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 20 21 #ifndef __ASSEMBLY__ 22 extern unsigned long get_clock_freq(void); 23 #endif 24 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 25 26 /* 27 * These can be toggled for performance analysis, otherwise use default. 28 */ 29 #define CONFIG_L2_CACHE /* toggle L2 cache */ 30 #define CONFIG_BTB /* toggle branch predition */ 31 32 #define CONFIG_SYS_CCSRBAR 0xe0000000 33 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 34 35 /* DDR Setup */ 36 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 37 #define CONFIG_DDR_SPD 38 39 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 40 41 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 42 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 43 44 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 45 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 46 47 /* I2C addresses of SPD EEPROMs */ 48 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 49 50 /* 51 * Make sure required options are set 52 */ 53 #ifndef CONFIG_SPD_EEPROM 54 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") 55 #endif 56 57 /* 58 * Local Bus Definitions 59 */ 60 61 /* 62 * FLASH on the Local Bus 63 * Two banks, 8M each, using the CFI driver. 64 * Boot from BR0/OR0 bank at 0xff00_0000 65 * Alternate BR1/OR1 bank at 0xff80_0000 66 * 67 * BR0, BR1: 68 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 69 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 70 * Port Size = 16 bits = BRx[19:20] = 10 71 * Use GPCM = BRx[24:26] = 000 72 * Valid = BRx[31] = 1 73 * 74 * 0 4 8 12 16 20 24 28 75 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 76 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 77 * 78 * OR0, OR1: 79 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 80 * Reserved ORx[17:18] = 11, confusion here? 81 * CSNT = ORx[20] = 1 82 * ACS = half cycle delay = ORx[21:22] = 11 83 * SCY = 6 = ORx[24:27] = 0110 84 * TRLX = use relaxed timing = ORx[29] = 1 85 * EAD = use external address latch delay = OR[31] = 1 86 * 87 * 0 4 8 12 16 20 24 28 88 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 89 */ 90 91 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */ 92 93 #define CONFIG_SYS_BR0_PRELIM 0xff801001 94 #define CONFIG_SYS_BR1_PRELIM 0xff001001 95 96 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 97 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 98 99 #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} 100 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 101 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 102 #undef CONFIG_SYS_FLASH_CHECKSUM 103 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 104 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 105 106 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 107 108 #define CONFIG_SYS_FLASH_EMPTY_INFO 109 110 /* 111 * SDRAM on the Local Bus 112 */ 113 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 114 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 115 116 /* 117 * Base Register 2 and Option Register 2 configure SDRAM. 118 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 119 * 120 * For BR2, need: 121 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 122 * port-size = 32-bits = BR2[19:20] = 11 123 * no parity checking = BR2[21:22] = 00 124 * SDRAM for MSEL = BR2[24:26] = 011 125 * Valid = BR[31] = 1 126 * 127 * 0 4 8 12 16 20 24 28 128 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 129 * 130 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 131 * FIXME: the top 17 bits of BR2. 132 */ 133 134 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 135 136 /* 137 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 138 * 139 * For OR2, need: 140 * 64MB mask for AM, OR2[0:7] = 1111 1100 141 * XAM, OR2[17:18] = 11 142 * 9 columns OR2[19-21] = 010 143 * 13 rows OR2[23-25] = 100 144 * EAD set for extra time OR[31] = 1 145 * 146 * 0 4 8 12 16 20 24 28 147 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 148 */ 149 150 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 151 152 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 153 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 154 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 155 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 156 157 /* 158 * Common settings for all Local Bus SDRAM commands. 159 * At run time, either BSMA1516 (for CPU 1.1) 160 * or BSMA1617 (for CPU 1.0) (old) 161 * is OR'ed in too. 162 */ 163 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 164 | LSDMR_PRETOACT7 \ 165 | LSDMR_ACTTORW7 \ 166 | LSDMR_BL8 \ 167 | LSDMR_WRC4 \ 168 | LSDMR_CL3 \ 169 | LSDMR_RFEN \ 170 ) 171 172 /* 173 * The CADMUS registers are connected to CS3 on CDS. 174 * The new memory map places CADMUS at 0xf8000000. 175 * 176 * For BR3, need: 177 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 178 * port-size = 8-bits = BR[19:20] = 01 179 * no parity checking = BR[21:22] = 00 180 * GPMC for MSEL = BR[24:26] = 000 181 * Valid = BR[31] = 1 182 * 183 * 0 4 8 12 16 20 24 28 184 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 185 * 186 * For OR3, need: 187 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 188 * disable buffer ctrl OR[19] = 0 189 * CSNT OR[20] = 1 190 * ACS OR[21:22] = 11 191 * XACS OR[23] = 1 192 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 193 * SETA OR[28] = 0 194 * TRLX OR[29] = 1 195 * EHTR OR[30] = 1 196 * EAD extra time OR[31] = 1 197 * 198 * 0 4 8 12 16 20 24 28 199 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 200 */ 201 202 #define CONFIG_FSL_CADMUS 203 204 #define CADMUS_BASE_ADDR 0xf8000000 205 #define CONFIG_SYS_BR3_PRELIM 0xf8000801 206 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 207 208 #define CONFIG_SYS_INIT_RAM_LOCK 1 209 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 210 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 211 212 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 213 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 214 215 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 216 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 217 218 /* Serial Port */ 219 #define CONFIG_SYS_NS16550_SERIAL 220 #define CONFIG_SYS_NS16550_REG_SIZE 1 221 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 222 223 #define CONFIG_SYS_BAUDRATE_TABLE \ 224 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 225 226 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 227 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 228 229 /* 230 * I2C 231 */ 232 #define CONFIG_SYS_I2C 233 #define CONFIG_SYS_I2C_FSL 234 #define CONFIG_SYS_FSL_I2C_SPEED 400000 235 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 236 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 237 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 238 239 /* EEPROM */ 240 #define CONFIG_ID_EEPROM 241 #define CONFIG_SYS_I2C_EEPROM_CCID 242 #define CONFIG_SYS_ID_EEPROM 243 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 244 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 245 246 /* 247 * General PCI 248 * Memory space is mapped 1-1, but I/O space must start from 0. 249 */ 250 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 251 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 252 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 253 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 254 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 255 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 256 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 257 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ 258 259 #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 260 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 261 #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 262 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ 263 #define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000 264 #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 265 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 266 #define CONFIG_SYS_PCI2_IO_SIZE 0x100000 /* 1M */ 267 268 #ifdef CONFIG_LEGACY 269 #define BRIDGE_ID 17 270 #define VIA_ID 2 271 #else 272 #define BRIDGE_ID 28 273 #define VIA_ID 4 274 #endif 275 276 #if defined(CONFIG_PCI) 277 278 #define CONFIG_MPC85XX_PCI2 279 280 281 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 282 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 283 284 #endif /* CONFIG_PCI */ 285 286 #if defined(CONFIG_TSEC_ENET) 287 288 #define CONFIG_TSEC1 1 289 #define CONFIG_TSEC1_NAME "TSEC0" 290 #define CONFIG_TSEC2 1 291 #define CONFIG_TSEC2_NAME "TSEC1" 292 #define TSEC1_PHY_ADDR 0 293 #define TSEC2_PHY_ADDR 1 294 #define TSEC1_PHYIDX 0 295 #define TSEC2_PHYIDX 0 296 #define TSEC1_FLAGS TSEC_GIGABIT 297 #define TSEC2_FLAGS TSEC_GIGABIT 298 299 /* Options are: TSEC[0-1] */ 300 #define CONFIG_ETHPRIME "TSEC0" 301 302 #endif /* CONFIG_TSEC_ENET */ 303 304 /* 305 * Environment 306 */ 307 308 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 309 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 310 311 /* 312 * BOOTP options 313 */ 314 #define CONFIG_BOOTP_BOOTFILESIZE 315 316 #undef CONFIG_WATCHDOG /* watchdog disabled */ 317 318 /* 319 * Miscellaneous configurable options 320 */ 321 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 322 323 /* 324 * For booting Linux, the board info and command line data 325 * have to be in the first 64 MB of memory, since this is 326 * the maximum mapped by the Linux kernel during initialization. 327 */ 328 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 329 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 330 331 #if defined(CONFIG_CMD_KGDB) 332 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 333 #endif 334 335 /* 336 * Environment Configuration 337 */ 338 339 /* The mac addresses for all ethernet interface */ 340 #if defined(CONFIG_TSEC_ENET) 341 #define CONFIG_HAS_ETH0 342 #define CONFIG_HAS_ETH1 343 #define CONFIG_HAS_ETH2 344 #endif 345 346 #define CONFIG_IPADDR 192.168.1.253 347 348 #define CONFIG_HOSTNAME "unknown" 349 #define CONFIG_ROOTPATH "/nfsroot" 350 #define CONFIG_BOOTFILE "your.uImage" 351 352 #define CONFIG_SERVERIP 192.168.1.1 353 #define CONFIG_GATEWAYIP 192.168.1.1 354 #define CONFIG_NETMASK 255.255.255.0 355 356 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 357 358 #define CONFIG_EXTRA_ENV_SETTINGS \ 359 "netdev=eth0\0" \ 360 "consoledev=ttyS1\0" \ 361 "ramdiskaddr=600000\0" \ 362 "ramdiskfile=your.ramdisk.u-boot\0" \ 363 "fdtaddr=400000\0" \ 364 "fdtfile=your.fdt.dtb\0" 365 366 #define CONFIG_NFSBOOTCOMMAND \ 367 "setenv bootargs root=/dev/nfs rw " \ 368 "nfsroot=$serverip:$rootpath " \ 369 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 370 "console=$consoledev,$baudrate $othbootargs;" \ 371 "tftp $loadaddr $bootfile;" \ 372 "tftp $fdtaddr $fdtfile;" \ 373 "bootm $loadaddr - $fdtaddr" 374 375 #define CONFIG_RAMBOOTCOMMAND \ 376 "setenv bootargs root=/dev/ram rw " \ 377 "console=$consoledev,$baudrate $othbootargs;" \ 378 "tftp $ramdiskaddr $ramdiskfile;" \ 379 "tftp $loadaddr $bootfile;" \ 380 "bootm $loadaddr $ramdiskaddr" 381 382 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 383 384 #endif /* __CONFIG_H */ 385