1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2004, 2011 Freescale Semiconductor. 4 */ 5 6 /* 7 * mpc8555cds board configuration file 8 * 9 * Please refer to doc/README.mpc85xxcds for more info. 10 * 11 */ 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 /* High Level Configuration Options */ 16 #define CONFIG_CPM2 1 /* has CPM2 */ 17 18 #define CONFIG_PCI_INDIRECT_BRIDGE 19 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 20 21 #ifndef __ASSEMBLY__ 22 extern unsigned long get_clock_freq(void); 23 #endif 24 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 25 26 /* 27 * These can be toggled for performance analysis, otherwise use default. 28 */ 29 #define CONFIG_L2_CACHE /* toggle L2 cache */ 30 #define CONFIG_BTB /* toggle branch predition */ 31 32 #define CONFIG_SYS_CCSRBAR 0xe0000000 33 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 34 35 /* DDR Setup */ 36 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 37 #define CONFIG_DDR_SPD 38 39 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 40 41 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 42 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 43 44 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 45 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 46 47 /* I2C addresses of SPD EEPROMs */ 48 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 49 50 /* Make sure required options are set */ 51 #ifndef CONFIG_SPD_EEPROM 52 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") 53 #endif 54 55 /* 56 * Local Bus Definitions 57 */ 58 59 /* 60 * FLASH on the Local Bus 61 * Two banks, 8M each, using the CFI driver. 62 * Boot from BR0/OR0 bank at 0xff00_0000 63 * Alternate BR1/OR1 bank at 0xff80_0000 64 * 65 * BR0, BR1: 66 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 67 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 68 * Port Size = 16 bits = BRx[19:20] = 10 69 * Use GPCM = BRx[24:26] = 000 70 * Valid = BRx[31] = 1 71 * 72 * 0 4 8 12 16 20 24 28 73 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 74 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 75 * 76 * OR0, OR1: 77 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 78 * Reserved ORx[17:18] = 11, confusion here? 79 * CSNT = ORx[20] = 1 80 * ACS = half cycle delay = ORx[21:22] = 11 81 * SCY = 6 = ORx[24:27] = 0110 82 * TRLX = use relaxed timing = ORx[29] = 1 83 * EAD = use external address latch delay = OR[31] = 1 84 * 85 * 0 4 8 12 16 20 24 28 86 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 87 */ 88 89 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */ 90 91 #define CONFIG_SYS_BR0_PRELIM 0xff801001 92 #define CONFIG_SYS_BR1_PRELIM 0xff001001 93 94 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 95 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 96 97 #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} 98 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 99 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 100 #undef CONFIG_SYS_FLASH_CHECKSUM 101 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 102 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 103 104 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 105 106 #define CONFIG_SYS_FLASH_EMPTY_INFO 107 108 /* 109 * SDRAM on the Local Bus 110 */ 111 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 112 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 113 114 /* 115 * Base Register 2 and Option Register 2 configure SDRAM. 116 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 117 * 118 * For BR2, need: 119 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 120 * port-size = 32-bits = BR2[19:20] = 11 121 * no parity checking = BR2[21:22] = 00 122 * SDRAM for MSEL = BR2[24:26] = 011 123 * Valid = BR[31] = 1 124 * 125 * 0 4 8 12 16 20 24 28 126 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 127 * 128 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 129 * FIXME: the top 17 bits of BR2. 130 */ 131 132 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 133 134 /* 135 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 136 * 137 * For OR2, need: 138 * 64MB mask for AM, OR2[0:7] = 1111 1100 139 * XAM, OR2[17:18] = 11 140 * 9 columns OR2[19-21] = 010 141 * 13 rows OR2[23-25] = 100 142 * EAD set for extra time OR[31] = 1 143 * 144 * 0 4 8 12 16 20 24 28 145 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 146 */ 147 148 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 149 150 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 151 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 152 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 153 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 154 155 /* 156 * Common settings for all Local Bus SDRAM commands. 157 * At run time, either BSMA1516 (for CPU 1.1) 158 * or BSMA1617 (for CPU 1.0) (old) 159 * is OR'ed in too. 160 */ 161 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 162 | LSDMR_PRETOACT7 \ 163 | LSDMR_ACTTORW7 \ 164 | LSDMR_BL8 \ 165 | LSDMR_WRC4 \ 166 | LSDMR_CL3 \ 167 | LSDMR_RFEN \ 168 ) 169 170 /* 171 * The CADMUS registers are connected to CS3 on CDS. 172 * The new memory map places CADMUS at 0xf8000000. 173 * 174 * For BR3, need: 175 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 176 * port-size = 8-bits = BR[19:20] = 01 177 * no parity checking = BR[21:22] = 00 178 * GPMC for MSEL = BR[24:26] = 000 179 * Valid = BR[31] = 1 180 * 181 * 0 4 8 12 16 20 24 28 182 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 183 * 184 * For OR3, need: 185 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 186 * disable buffer ctrl OR[19] = 0 187 * CSNT OR[20] = 1 188 * ACS OR[21:22] = 11 189 * XACS OR[23] = 1 190 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 191 * SETA OR[28] = 0 192 * TRLX OR[29] = 1 193 * EHTR OR[30] = 1 194 * EAD extra time OR[31] = 1 195 * 196 * 0 4 8 12 16 20 24 28 197 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 198 */ 199 200 #define CONFIG_FSL_CADMUS 201 202 #define CADMUS_BASE_ADDR 0xf8000000 203 #define CONFIG_SYS_BR3_PRELIM 0xf8000801 204 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 205 206 #define CONFIG_SYS_INIT_RAM_LOCK 1 207 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 208 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 209 210 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 211 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 212 213 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 214 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 215 216 /* Serial Port */ 217 #define CONFIG_SYS_NS16550_SERIAL 218 #define CONFIG_SYS_NS16550_REG_SIZE 1 219 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 220 221 #define CONFIG_SYS_BAUDRATE_TABLE \ 222 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 223 224 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 225 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 226 227 /* 228 * I2C 229 */ 230 #define CONFIG_SYS_I2C 231 #define CONFIG_SYS_I2C_FSL 232 #define CONFIG_SYS_FSL_I2C_SPEED 400000 233 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 234 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 235 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 236 237 /* EEPROM */ 238 #define CONFIG_ID_EEPROM 239 #define CONFIG_SYS_I2C_EEPROM_CCID 240 #define CONFIG_SYS_ID_EEPROM 241 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 242 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 243 244 /* 245 * General PCI 246 * Addresses are mapped 1-1. 247 */ 248 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 249 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 250 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 251 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 252 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 253 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 254 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 255 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 256 257 #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 258 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 259 #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 260 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ 261 #define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000 262 #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 263 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 264 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 265 266 #ifdef CONFIG_LEGACY 267 #define BRIDGE_ID 17 268 #define VIA_ID 2 269 #else 270 #define BRIDGE_ID 28 271 #define VIA_ID 4 272 #endif 273 274 #if defined(CONFIG_PCI) 275 276 #define CONFIG_MPC85XX_PCI2 277 278 279 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 280 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 281 282 #endif /* CONFIG_PCI */ 283 284 #if defined(CONFIG_TSEC_ENET) 285 286 #define CONFIG_TSEC1 1 287 #define CONFIG_TSEC1_NAME "TSEC0" 288 #define CONFIG_TSEC2 1 289 #define CONFIG_TSEC2_NAME "TSEC1" 290 #define TSEC1_PHY_ADDR 0 291 #define TSEC2_PHY_ADDR 1 292 #define TSEC1_PHYIDX 0 293 #define TSEC2_PHYIDX 0 294 #define TSEC1_FLAGS TSEC_GIGABIT 295 #define TSEC2_FLAGS TSEC_GIGABIT 296 297 /* Options are: TSEC[0-1] */ 298 #define CONFIG_ETHPRIME "TSEC0" 299 300 #endif /* CONFIG_TSEC_ENET */ 301 302 /* 303 * Environment 304 */ 305 306 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 307 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 308 309 /* 310 * BOOTP options 311 */ 312 #define CONFIG_BOOTP_BOOTFILESIZE 313 314 #undef CONFIG_WATCHDOG /* watchdog disabled */ 315 316 /* 317 * Miscellaneous configurable options 318 */ 319 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 320 321 /* 322 * For booting Linux, the board info and command line data 323 * have to be in the first 64 MB of memory, since this is 324 * the maximum mapped by the Linux kernel during initialization. 325 */ 326 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 327 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 328 329 #if defined(CONFIG_CMD_KGDB) 330 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 331 #endif 332 333 /* 334 * Environment Configuration 335 */ 336 #if defined(CONFIG_TSEC_ENET) 337 #define CONFIG_HAS_ETH0 338 #define CONFIG_HAS_ETH1 339 #define CONFIG_HAS_ETH2 340 #endif 341 342 #define CONFIG_IPADDR 192.168.1.253 343 344 #define CONFIG_HOSTNAME "unknown" 345 #define CONFIG_ROOTPATH "/nfsroot" 346 #define CONFIG_BOOTFILE "your.uImage" 347 348 #define CONFIG_SERVERIP 192.168.1.1 349 #define CONFIG_GATEWAYIP 192.168.1.1 350 #define CONFIG_NETMASK 255.255.255.0 351 352 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 353 354 #define CONFIG_EXTRA_ENV_SETTINGS \ 355 "netdev=eth0\0" \ 356 "consoledev=ttyS1\0" \ 357 "ramdiskaddr=600000\0" \ 358 "ramdiskfile=your.ramdisk.u-boot\0" \ 359 "fdtaddr=400000\0" \ 360 "fdtfile=your.fdt.dtb\0" 361 362 #define CONFIG_NFSBOOTCOMMAND \ 363 "setenv bootargs root=/dev/nfs rw " \ 364 "nfsroot=$serverip:$rootpath " \ 365 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 366 "console=$consoledev,$baudrate $othbootargs;" \ 367 "tftp $loadaddr $bootfile;" \ 368 "tftp $fdtaddr $fdtfile;" \ 369 "bootm $loadaddr - $fdtaddr" 370 371 #define CONFIG_RAMBOOTCOMMAND \ 372 "setenv bootargs root=/dev/ram rw " \ 373 "console=$consoledev,$baudrate $othbootargs;" \ 374 "tftp $ramdiskaddr $ramdiskfile;" \ 375 "tftp $loadaddr $bootfile;" \ 376 "bootm $loadaddr $ramdiskaddr" 377 378 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 379 380 #endif /* __CONFIG_H */ 381