1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2004, 2011 Freescale Semiconductor. 4 * (C) Copyright 2002,2003 Motorola,Inc. 5 * Xianghua Xiao <X.Xiao@motorola.com> 6 */ 7 8 /* 9 * mpc8560ads board configuration file 10 * 11 * Please refer to doc/README.mpc85xx for more info. 12 * 13 * Make sure you change the MAC address and other network params first, 14 * search for CONFIG_SERVERIP, etc. in this file. 15 */ 16 17 #ifndef __CONFIG_H 18 #define __CONFIG_H 19 20 #include <linux/delay.h> 21 22 /* High Level Configuration Options */ 23 #define CONFIG_CPM2 1 /* has CPM2 */ 24 25 /* 26 * default CCARBAR is at 0xff700000 27 * assume U-Boot is less than 0.5MB 28 */ 29 30 #define CONFIG_PCI_INDIRECT_BRIDGE 31 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 32 #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ 33 #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ 34 35 /* 36 * sysclk for MPC85xx 37 * 38 * Two valid values are: 39 * 33000000 40 * 66000000 41 * 42 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 43 * is likely the desired value here, so that is now the default. 44 * The board, however, can run at 66MHz. In any event, this value 45 * must match the settings of some switches. Details can be found 46 * in the README.mpc85xxads. 47 */ 48 49 #ifndef CONFIG_SYS_CLK_FREQ 50 #define CONFIG_SYS_CLK_FREQ 33000000 51 #endif 52 53 /* 54 * These can be toggled for performance analysis, otherwise use default. 55 */ 56 #define CONFIG_L2_CACHE /* toggle L2 cache */ 57 #define CONFIG_BTB /* toggle branch predition */ 58 59 #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ 60 61 #define CONFIG_SYS_CCSRBAR 0xe0000000 62 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 63 64 /* DDR Setup */ 65 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 66 #define CONFIG_DDR_SPD 67 68 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 69 70 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 71 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 72 73 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 74 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 75 76 /* I2C addresses of SPD EEPROMs */ 77 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 78 79 /* These are used when DDR doesn't use SPD. */ 80 #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ 81 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ 82 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 83 #define CONFIG_SYS_DDR_TIMING_1 0x37344321 84 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 85 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 86 #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ 87 #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ 88 89 /* 90 * SDRAM on the Local Bus 91 */ 92 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 93 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 94 95 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 96 #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ 97 98 #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ 99 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 100 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ 101 #undef CONFIG_SYS_FLASH_CHECKSUM 102 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 103 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 104 105 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 106 107 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 108 #define CONFIG_SYS_RAMBOOT 109 #else 110 #undef CONFIG_SYS_RAMBOOT 111 #endif 112 113 #define CONFIG_SYS_FLASH_EMPTY_INFO 114 115 /* 116 * Local Bus Definitions 117 */ 118 119 /* 120 * Base Register 2 and Option Register 2 configure SDRAM. 121 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 122 * 123 * For BR2, need: 124 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 125 * port-size = 32-bits = BR2[19:20] = 11 126 * no parity checking = BR2[21:22] = 00 127 * SDRAM for MSEL = BR2[24:26] = 011 128 * Valid = BR[31] = 1 129 * 130 * 0 4 8 12 16 20 24 28 131 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 132 * 133 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 134 * FIXME: the top 17 bits of BR2. 135 */ 136 137 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 138 139 /* 140 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 141 * 142 * For OR2, need: 143 * 64MB mask for AM, OR2[0:7] = 1111 1100 144 * XAM, OR2[17:18] = 11 145 * 9 columns OR2[19-21] = 010 146 * 13 rows OR2[23-25] = 100 147 * EAD set for extra time OR[31] = 1 148 * 149 * 0 4 8 12 16 20 24 28 150 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 151 */ 152 153 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 154 155 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 156 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 157 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 158 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ 159 160 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \ 161 | LSDMR_RFCR5 \ 162 | LSDMR_PRETOACT3 \ 163 | LSDMR_ACTTORW3 \ 164 | LSDMR_BL8 \ 165 | LSDMR_WRC2 \ 166 | LSDMR_CL3 \ 167 | LSDMR_RFEN \ 168 ) 169 170 /* 171 * SDRAM Controller configuration sequence. 172 */ 173 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 174 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 175 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 176 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 177 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 178 179 /* 180 * 32KB, 8-bit wide for ADS config reg 181 */ 182 #define CONFIG_SYS_BR4_PRELIM 0xf8000801 183 #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 184 #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) 185 186 #define CONFIG_SYS_INIT_RAM_LOCK 1 187 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 188 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 189 190 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 191 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 192 193 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 194 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 195 196 /* Serial Port */ 197 #define CONFIG_CONS_ON_SCC /* define if console on SCC */ 198 #undef CONFIG_CONS_NONE /* define if console on something else */ 199 200 #define CONFIG_SYS_BAUDRATE_TABLE \ 201 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 202 203 /* 204 * I2C 205 */ 206 #define CONFIG_SYS_I2C 207 #define CONFIG_SYS_I2C_FSL 208 #define CONFIG_SYS_FSL_I2C_SPEED 400000 209 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 210 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 211 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 212 213 /* RapidIO MMU */ 214 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ 215 #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ 216 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 217 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ 218 219 /* 220 * General PCI 221 * Memory space is mapped 1-1, but I/O space must start from 0. 222 */ 223 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 224 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 225 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 226 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 227 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 228 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 229 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 230 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ 231 232 #if defined(CONFIG_PCI) 233 234 #if !defined(CONFIG_PCI_PNP) 235 #define PCI_ENET0_IOADDR 0xe0000000 236 #define PCI_ENET0_MEMADDR 0xe0000000 237 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 238 #endif 239 240 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 241 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 242 243 #endif /* CONFIG_PCI */ 244 245 #ifdef CONFIG_TSEC_ENET 246 247 #define CONFIG_TSEC1 1 248 #define CONFIG_TSEC1_NAME "TSEC0" 249 #define CONFIG_TSEC2 1 250 #define CONFIG_TSEC2_NAME "TSEC1" 251 #define TSEC1_PHY_ADDR 0 252 #define TSEC2_PHY_ADDR 1 253 #define TSEC1_PHYIDX 0 254 #define TSEC2_PHYIDX 0 255 #define TSEC1_FLAGS TSEC_GIGABIT 256 #define TSEC2_FLAGS TSEC_GIGABIT 257 258 /* Options are: TSEC[0-1] */ 259 #define CONFIG_ETHPRIME "TSEC0" 260 261 #endif /* CONFIG_TSEC_ENET */ 262 263 #ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */ 264 265 #undef CONFIG_ETHER_NONE /* define if ether on something else */ 266 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ 267 268 #if (CONFIG_ETHER_INDEX == 2) 269 /* 270 * - Rx-CLK is CLK13 271 * - Tx-CLK is CLK14 272 * - Select bus for bd/buffers 273 * - Full duplex 274 */ 275 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) 276 #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) 277 #define CONFIG_SYS_CPMFCR_RAMTYPE 0 278 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) 279 #define FETH2_RST 0x01 280 #elif (CONFIG_ETHER_INDEX == 3) 281 /* need more definitions here for FE3 */ 282 #define FETH3_RST 0x80 283 #endif /* CONFIG_ETHER_INDEX */ 284 285 /* 286 * GPIO pins used for bit-banged MII communications 287 */ 288 #define MDIO_PORT 2 /* Port C */ 289 #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ 290 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) 291 #define MDC_DECLARE MDIO_DECLARE 292 293 #define MDIO_ACTIVE (iop->pdir |= 0x00400000) 294 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) 295 #define MDIO_READ ((iop->pdat & 0x00400000) != 0) 296 297 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ 298 else iop->pdat &= ~0x00400000 299 300 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ 301 else iop->pdat &= ~0x00200000 302 303 #define MIIDELAY udelay(1) 304 305 #endif 306 307 /* 308 * Environment 309 */ 310 311 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 312 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 313 314 /* 315 * BOOTP options 316 */ 317 #define CONFIG_BOOTP_BOOTFILESIZE 318 319 #undef CONFIG_WATCHDOG /* watchdog disabled */ 320 321 /* 322 * Miscellaneous configurable options 323 */ 324 #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ 325 326 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 327 328 /* 329 * For booting Linux, the board info and command line data 330 * have to be in the first 64 MB of memory, since this is 331 * the maximum mapped by the Linux kernel during initialization. 332 */ 333 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 334 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 335 336 #if defined(CONFIG_CMD_KGDB) 337 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 338 #endif 339 340 /* 341 * Environment Configuration 342 */ 343 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) 344 #define CONFIG_HAS_ETH0 345 #define CONFIG_HAS_ETH1 346 #define CONFIG_HAS_ETH2 347 #define CONFIG_HAS_ETH3 348 #endif 349 350 #define CONFIG_IPADDR 192.168.1.253 351 352 #define CONFIG_HOSTNAME "unknown" 353 #define CONFIG_ROOTPATH "/nfsroot" 354 #define CONFIG_BOOTFILE "your.uImage" 355 356 #define CONFIG_SERVERIP 192.168.1.1 357 #define CONFIG_GATEWAYIP 192.168.1.1 358 #define CONFIG_NETMASK 255.255.255.0 359 360 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 361 362 #define CONFIG_EXTRA_ENV_SETTINGS \ 363 "netdev=eth0\0" \ 364 "consoledev=ttyCPM\0" \ 365 "ramdiskaddr=1000000\0" \ 366 "ramdiskfile=your.ramdisk.u-boot\0" \ 367 "fdtaddr=400000\0" \ 368 "fdtfile=mpc8560ads.dtb\0" 369 370 #define CONFIG_NFSBOOTCOMMAND \ 371 "setenv bootargs root=/dev/nfs rw " \ 372 "nfsroot=$serverip:$rootpath " \ 373 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 374 "console=$consoledev,$baudrate $othbootargs;" \ 375 "tftp $loadaddr $bootfile;" \ 376 "tftp $fdtaddr $fdtfile;" \ 377 "bootm $loadaddr - $fdtaddr" 378 379 #define CONFIG_RAMBOOTCOMMAND \ 380 "setenv bootargs root=/dev/ram rw " \ 381 "console=$consoledev,$baudrate $othbootargs;" \ 382 "tftp $ramdiskaddr $ramdiskfile;" \ 383 "tftp $loadaddr $bootfile;" \ 384 "tftp $fdtaddr $fdtfile;" \ 385 "bootm $loadaddr $ramdiskaddr $fdtaddr" 386 387 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 388 389 #endif /* __CONFIG_H */ 390