1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 * Copyright 2020 NXP 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #include <linux/stringify.h> 11 12 /* 13 * T104x RDB board configuration file 14 */ 15 #include <asm/config_mpc85xx.h> 16 17 #ifdef CONFIG_RAMBOOT_PBL 18 19 #ifndef CONFIG_NXP_ESBC 20 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg 21 #else 22 #define CONFIG_SYS_FSL_PBL_PBI \ 23 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg 24 #endif 25 26 #define CONFIG_SPL_FLUSH_IMAGE 27 #define CONFIG_SPL_PAD_TO 0x40000 28 #define CONFIG_SPL_MAX_SIZE 0x28000 29 #ifdef CONFIG_SPL_BUILD 30 #define CONFIG_SPL_SKIP_RELOCATE 31 #define CONFIG_SPL_COMMON_INIT_DDR 32 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 33 #endif 34 #define RESET_VECTOR_OFFSET 0x27FFC 35 #define BOOT_PAGE_OFFSET 0x27000 36 37 #ifdef CONFIG_MTD_RAW_NAND 38 #ifdef CONFIG_NXP_ESBC 39 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 40 /* 41 * HDR would be appended at end of image and copied to DDR along 42 * with U-Boot image. 43 */ 44 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ 45 CONFIG_U_BOOT_HDR_SIZE) 46 #else 47 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 48 #endif 49 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 50 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 51 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 52 #ifdef CONFIG_TARGET_T1040RDB 53 #define CONFIG_SYS_FSL_PBL_RCW \ 54 $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg 55 #endif 56 #ifdef CONFIG_TARGET_T1042RDB_PI 57 #define CONFIG_SYS_FSL_PBL_RCW \ 58 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg 59 #endif 60 #ifdef CONFIG_TARGET_T1042RDB 61 #define CONFIG_SYS_FSL_PBL_RCW \ 62 $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg 63 #endif 64 #ifdef CONFIG_TARGET_T1040D4RDB 65 #define CONFIG_SYS_FSL_PBL_RCW \ 66 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg 67 #endif 68 #ifdef CONFIG_TARGET_T1042D4RDB 69 #define CONFIG_SYS_FSL_PBL_RCW \ 70 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg 71 #endif 72 #endif 73 74 #ifdef CONFIG_SPIFLASH 75 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 76 #define CONFIG_SPL_SPI_FLASH_MINIMAL 77 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 78 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 79 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 80 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 81 #ifndef CONFIG_SPL_BUILD 82 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 83 #endif 84 #ifdef CONFIG_TARGET_T1040RDB 85 #define CONFIG_SYS_FSL_PBL_RCW \ 86 $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg 87 #endif 88 #ifdef CONFIG_TARGET_T1042RDB_PI 89 #define CONFIG_SYS_FSL_PBL_RCW \ 90 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg 91 #endif 92 #ifdef CONFIG_TARGET_T1042RDB 93 #define CONFIG_SYS_FSL_PBL_RCW \ 94 $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg 95 #endif 96 #ifdef CONFIG_TARGET_T1040D4RDB 97 #define CONFIG_SYS_FSL_PBL_RCW \ 98 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg 99 #endif 100 #ifdef CONFIG_TARGET_T1042D4RDB 101 #define CONFIG_SYS_FSL_PBL_RCW \ 102 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg 103 #endif 104 #endif 105 106 #ifdef CONFIG_SDCARD 107 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 108 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 109 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 110 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 111 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 112 #ifndef CONFIG_SPL_BUILD 113 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 114 #endif 115 #ifdef CONFIG_TARGET_T1040RDB 116 #define CONFIG_SYS_FSL_PBL_RCW \ 117 $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg 118 #endif 119 #ifdef CONFIG_TARGET_T1042RDB_PI 120 #define CONFIG_SYS_FSL_PBL_RCW \ 121 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg 122 #endif 123 #ifdef CONFIG_TARGET_T1042RDB 124 #define CONFIG_SYS_FSL_PBL_RCW \ 125 $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg 126 #endif 127 #ifdef CONFIG_TARGET_T1040D4RDB 128 #define CONFIG_SYS_FSL_PBL_RCW \ 129 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg 130 #endif 131 #ifdef CONFIG_TARGET_T1042D4RDB 132 #define CONFIG_SYS_FSL_PBL_RCW \ 133 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg 134 #endif 135 #endif 136 137 #endif 138 139 /* High Level Configuration Options */ 140 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 141 142 /* support deep sleep */ 143 #define CONFIG_DEEP_SLEEP 144 145 #ifndef CONFIG_RESET_VECTOR_ADDRESS 146 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 147 #endif 148 149 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 150 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 151 #define CONFIG_PCIE1 /* PCIE controller 1 */ 152 #define CONFIG_PCIE2 /* PCIE controller 2 */ 153 #define CONFIG_PCIE3 /* PCIE controller 3 */ 154 #define CONFIG_PCIE4 /* PCIE controller 4 */ 155 156 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 157 158 #if defined(CONFIG_SPIFLASH) 159 #elif defined(CONFIG_MTD_RAW_NAND) 160 #ifdef CONFIG_NXP_ESBC 161 #define CONFIG_RAMBOOT_NAND 162 #define CONFIG_BOOTSCRIPT_COPY_RAM 163 #endif 164 #endif 165 166 #define CONFIG_SYS_CLK_FREQ 100000000 167 #define CONFIG_DDR_CLK_FREQ 66666666 168 169 /* 170 * These can be toggled for performance analysis, otherwise use default. 171 */ 172 #define CONFIG_SYS_CACHE_STASHING 173 #define CONFIG_BACKSIDE_L2_CACHE 174 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 175 #define CONFIG_BTB /* toggle branch predition */ 176 #define CONFIG_DDR_ECC 177 #ifdef CONFIG_DDR_ECC 178 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 179 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 180 #endif 181 182 #define CONFIG_ENABLE_36BIT_PHYS 183 184 /* 185 * Config the L3 Cache as L3 SRAM 186 */ 187 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 188 /* 189 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence 190 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address 191 * (CONFIG_SYS_INIT_L3_VADDR) will be different. 192 */ 193 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 194 #define CONFIG_SYS_L3_SIZE 256 << 10 195 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) 196 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 197 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 198 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 199 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 200 201 #define CONFIG_SYS_DCSRBAR 0xf0000000 202 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 203 204 /* 205 * DDR Setup 206 */ 207 #define CONFIG_VERY_BIG_RAM 208 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 209 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 210 211 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 212 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 213 214 #define CONFIG_DDR_SPD 215 216 #define CONFIG_SYS_SPD_BUS_NUM 0 217 #define SPD_EEPROM_ADDRESS 0x51 218 219 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 220 221 /* 222 * IFC Definitions 223 */ 224 #define CONFIG_SYS_FLASH_BASE 0xe8000000 225 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 226 227 #define CONFIG_SYS_NOR_CSPR_EXT (0xf) 228 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ 229 CSPR_PORT_SIZE_16 | \ 230 CSPR_MSEL_NOR | \ 231 CSPR_V) 232 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 233 234 /* 235 * TDM Definition 236 */ 237 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 238 239 /* NOR Flash Timing Params */ 240 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 241 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 242 FTIM0_NOR_TEADC(0x5) | \ 243 FTIM0_NOR_TEAHC(0x5)) 244 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 245 FTIM1_NOR_TRAD_NOR(0x1A) |\ 246 FTIM1_NOR_TSEQRAD_NOR(0x13)) 247 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 248 FTIM2_NOR_TCH(0x4) | \ 249 FTIM2_NOR_TWPH(0x0E) | \ 250 FTIM2_NOR_TWP(0x1c)) 251 #define CONFIG_SYS_NOR_FTIM3 0x0 252 253 #define CONFIG_SYS_FLASH_QUIET_TEST 254 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 255 256 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 257 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 258 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 259 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 260 261 #define CONFIG_SYS_FLASH_EMPTY_INFO 262 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 263 264 /* CPLD on IFC */ 265 #define CPLD_LBMAP_MASK 0x3F 266 #define CPLD_BANK_SEL_MASK 0x07 267 #define CPLD_BANK_OVERRIDE 0x40 268 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ 269 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ 270 #define CPLD_LBMAP_RESET 0xFF 271 #define CPLD_LBMAP_SHIFT 0x03 272 273 #if defined(CONFIG_TARGET_T1042RDB_PI) 274 #define CPLD_DIU_SEL_DFP 0x80 275 #elif defined(CONFIG_TARGET_T1042D4RDB) 276 #define CPLD_DIU_SEL_DFP 0xc0 277 #endif 278 279 #if defined(CONFIG_TARGET_T1040D4RDB) 280 #define CPLD_INT_MASK_ALL 0xFF 281 #define CPLD_INT_MASK_THERM 0x80 282 #define CPLD_INT_MASK_DVI_DFP 0x40 283 #define CPLD_INT_MASK_QSGMII1 0x20 284 #define CPLD_INT_MASK_QSGMII2 0x10 285 #define CPLD_INT_MASK_SGMI1 0x08 286 #define CPLD_INT_MASK_SGMI2 0x04 287 #define CPLD_INT_MASK_TDMR1 0x02 288 #define CPLD_INT_MASK_TDMR2 0x01 289 #endif 290 291 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 292 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 293 #define CONFIG_SYS_CSPR2_EXT (0xf) 294 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 295 | CSPR_PORT_SIZE_8 \ 296 | CSPR_MSEL_GPCM \ 297 | CSPR_V) 298 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 299 #define CONFIG_SYS_CSOR2 0x0 300 /* CPLD Timing parameters for IFC CS2 */ 301 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 302 FTIM0_GPCM_TEADC(0x0e) | \ 303 FTIM0_GPCM_TEAHC(0x0e)) 304 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 305 FTIM1_GPCM_TRAD(0x1f)) 306 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 307 FTIM2_GPCM_TCH(0x8) | \ 308 FTIM2_GPCM_TWP(0x1f)) 309 #define CONFIG_SYS_CS2_FTIM3 0x0 310 311 /* NAND Flash on IFC */ 312 #define CONFIG_NAND_FSL_IFC 313 #define CONFIG_SYS_NAND_BASE 0xff800000 314 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 315 316 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 317 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 318 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 319 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 320 | CSPR_V) 321 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 322 323 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 324 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 325 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 326 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 327 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 328 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ 329 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 330 331 #define CONFIG_SYS_NAND_ONFI_DETECTION 332 333 /* ONFI NAND Flash mode0 Timing Params */ 334 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 335 FTIM0_NAND_TWP(0x18) | \ 336 FTIM0_NAND_TWCHT(0x07) | \ 337 FTIM0_NAND_TWH(0x0a)) 338 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 339 FTIM1_NAND_TWBE(0x39) | \ 340 FTIM1_NAND_TRR(0x0e) | \ 341 FTIM1_NAND_TRP(0x18)) 342 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 343 FTIM2_NAND_TREH(0x0a) | \ 344 FTIM2_NAND_TWHRE(0x1e)) 345 #define CONFIG_SYS_NAND_FTIM3 0x0 346 347 #define CONFIG_SYS_NAND_DDR_LAW 11 348 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 349 #define CONFIG_SYS_MAX_NAND_DEVICE 1 350 351 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 352 353 #if defined(CONFIG_MTD_RAW_NAND) 354 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 355 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 356 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 357 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 358 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 359 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 360 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 361 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 362 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 363 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 364 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 365 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 366 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 367 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 368 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 369 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 370 #else 371 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 372 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 373 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 374 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 375 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 376 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 377 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 378 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 379 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 380 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 381 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 382 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 383 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 384 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 385 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 386 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 387 #endif 388 389 #ifdef CONFIG_SPL_BUILD 390 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 391 #else 392 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 393 #endif 394 395 #if defined(CONFIG_RAMBOOT_PBL) 396 #define CONFIG_SYS_RAMBOOT 397 #endif 398 399 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044 400 #if defined(CONFIG_MTD_RAW_NAND) 401 #define CONFIG_A008044_WORKAROUND 402 #endif 403 #endif 404 405 #define CONFIG_HWCONFIG 406 407 /* define to use L1 as initial stack */ 408 #define CONFIG_L1_INIT_RAM 409 #define CONFIG_SYS_INIT_RAM_LOCK 410 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 411 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 412 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 413 /* The assembler doesn't like typecast */ 414 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 415 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 416 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 417 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 418 419 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 420 GENERATED_GBL_DATA_SIZE) 421 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 422 423 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 424 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 425 426 /* Serial Port - controlled on board with jumper J8 427 * open - index 2 428 * shorted - index 1 429 */ 430 #define CONFIG_SYS_NS16550_SERIAL 431 #define CONFIG_SYS_NS16550_REG_SIZE 1 432 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 433 434 #define CONFIG_SYS_BAUDRATE_TABLE \ 435 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 436 437 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 438 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 439 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 440 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 441 442 #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB) 443 /* Video */ 444 #define CONFIG_FSL_DIU_FB 445 446 #ifdef CONFIG_FSL_DIU_FB 447 #define CONFIG_FSL_DIU_CH7301 448 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 449 #define CONFIG_VIDEO_LOGO 450 #define CONFIG_VIDEO_BMP_LOGO 451 #endif 452 #endif 453 454 /* I2C */ 455 #if !CONFIG_IS_ENABLED(DM_I2C) 456 #define CONFIG_SYS_I2C 457 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 458 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 459 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 460 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 461 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 462 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 463 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 464 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 465 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 466 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 467 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 468 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 469 #else 470 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM 471 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 472 #endif 473 474 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 475 /* I2C bus multiplexer */ 476 #define I2C_MUX_PCA_ADDR 0x70 477 #define I2C_MUX_CH_DEFAULT 0x8 478 479 #if defined(CONFIG_TARGET_T1042RDB_PI) || \ 480 defined(CONFIG_TARGET_T1040D4RDB) || \ 481 defined(CONFIG_TARGET_T1042D4RDB) 482 /* LDI/DVI Encoder for display */ 483 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 484 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 485 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0 486 487 /* 488 * RTC configuration 489 */ 490 #define RTC 491 #define CONFIG_RTC_DS1337 1 492 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 493 494 /*DVI encoder*/ 495 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 496 #endif 497 498 /* 499 * eSPI - Enhanced SPI 500 */ 501 502 /* 503 * General PCI 504 * Memory space is mapped 1-1, but I/O space must start from 0. 505 */ 506 507 #ifdef CONFIG_PCI 508 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 509 #ifdef CONFIG_PCIE1 510 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 511 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 512 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 513 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 514 #endif 515 516 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 517 #ifdef CONFIG_PCIE2 518 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 519 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 520 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 521 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 522 #endif 523 524 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 525 #ifdef CONFIG_PCIE3 526 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 527 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 528 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 529 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 530 #endif 531 532 /* controller 4, Base address 203000 */ 533 #ifdef CONFIG_PCIE4 534 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 535 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 536 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 537 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 538 #endif 539 540 #if !defined(CONFIG_DM_PCI) 541 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 542 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 543 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 544 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 545 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 546 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 547 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 548 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 549 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 550 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 551 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 552 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 553 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 554 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 555 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 556 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 557 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 558 #define CONFIG_PCI_INDIRECT_BRIDGE 559 #endif 560 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 561 #endif /* CONFIG_PCI */ 562 563 /* SATA */ 564 #define CONFIG_FSL_SATA_V2 565 #ifdef CONFIG_FSL_SATA_V2 566 #define CONFIG_SYS_SATA_MAX_DEVICE 1 567 #define CONFIG_SATA1 568 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 569 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 570 571 #define CONFIG_LBA48 572 #endif 573 574 /* 575 * USB 576 */ 577 #define CONFIG_HAS_FSL_DR_USB 578 579 #ifdef CONFIG_HAS_FSL_DR_USB 580 #ifdef CONFIG_USB_EHCI_HCD 581 #define CONFIG_USB_EHCI_FSL 582 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 583 #endif 584 #endif 585 586 #ifdef CONFIG_MMC 587 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 588 #endif 589 590 /* Qman/Bman */ 591 #ifndef CONFIG_NOBQFMAN 592 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 593 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 594 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 595 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 596 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 597 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 598 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 599 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 600 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 601 CONFIG_SYS_BMAN_CENA_SIZE) 602 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 603 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 604 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 605 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 606 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 607 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 608 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 609 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 610 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 611 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 612 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 613 CONFIG_SYS_QMAN_CENA_SIZE) 614 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 615 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 616 617 #define CONFIG_SYS_DPAA_FMAN 618 #define CONFIG_SYS_DPAA_PME 619 620 #define CONFIG_U_QE 621 622 /* Default address of microcode for the Linux Fman driver */ 623 #if defined(CONFIG_SPIFLASH) 624 /* 625 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 626 * env, so we got 0x110000. 627 */ 628 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 629 #elif defined(CONFIG_SDCARD) 630 /* 631 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 632 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 633 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 634 */ 635 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 636 #elif defined(CONFIG_MTD_RAW_NAND) 637 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 638 #else 639 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 640 #endif 641 642 #if defined(CONFIG_SPIFLASH) 643 #define CONFIG_SYS_QE_FW_ADDR 0x130000 644 #elif defined(CONFIG_SDCARD) 645 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 646 #elif defined(CONFIG_MTD_RAW_NAND) 647 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 648 #else 649 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 650 #endif 651 652 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 653 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 654 #endif /* CONFIG_NOBQFMAN */ 655 656 #ifdef CONFIG_FMAN_ENET 657 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB) 658 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 659 #elif defined(CONFIG_TARGET_T1040D4RDB) 660 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 661 #elif defined(CONFIG_TARGET_T1042D4RDB) 662 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 663 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 664 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 665 #endif 666 667 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) 668 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 669 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 670 #else 671 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 672 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 673 #endif 674 675 /* Enable VSC9953 L2 Switch driver on T1040 SoC */ 676 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB) 677 #define CONFIG_VSC9953 678 #ifdef CONFIG_TARGET_T1040RDB 679 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 680 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 681 #else 682 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 683 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c 684 #endif 685 #endif 686 687 #define CONFIG_ETHPRIME "FM1@DTSEC4" 688 #endif 689 690 /* 691 * Environment 692 */ 693 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 694 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 695 696 /* 697 * Miscellaneous configurable options 698 */ 699 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 700 701 /* 702 * For booting Linux, the board info and command line data 703 * have to be in the first 64 MB of memory, since this is 704 * the maximum mapped by the Linux kernel during initialization. 705 */ 706 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 707 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 708 709 #ifdef CONFIG_CMD_KGDB 710 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 711 #endif 712 713 /* 714 * Dynamic MTD Partition support with mtdparts 715 */ 716 717 /* 718 * Environment Configuration 719 */ 720 #define CONFIG_ROOTPATH "/opt/nfsroot" 721 #define CONFIG_BOOTFILE "uImage" 722 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 723 724 /* default location for tftp and bootm */ 725 #define CONFIG_LOADADDR 1000000 726 727 #define __USB_PHY_TYPE utmi 728 #define RAMDISKFILE "t104xrdb/ramdisk.uboot" 729 730 #ifdef CONFIG_TARGET_T1040RDB 731 #define FDTFILE "t1040rdb/t1040rdb.dtb" 732 #elif defined(CONFIG_TARGET_T1042RDB_PI) 733 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" 734 #elif defined(CONFIG_TARGET_T1042RDB) 735 #define FDTFILE "t1042rdb/t1042rdb.dtb" 736 #elif defined(CONFIG_TARGET_T1040D4RDB) 737 #define FDTFILE "t1042rdb/t1040d4rdb.dtb" 738 #elif defined(CONFIG_TARGET_T1042D4RDB) 739 #define FDTFILE "t1042rdb/t1042d4rdb.dtb" 740 #endif 741 742 #ifdef CONFIG_FSL_DIU_FB 743 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" 744 #else 745 #define DIU_ENVIRONMENT 746 #endif 747 748 #define CONFIG_EXTRA_ENV_SETTINGS \ 749 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ 750 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 751 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 752 "netdev=eth0\0" \ 753 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ 754 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 755 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 756 "tftpflash=tftpboot $loadaddr $uboot && " \ 757 "protect off $ubootaddr +$filesize && " \ 758 "erase $ubootaddr +$filesize && " \ 759 "cp.b $loadaddr $ubootaddr $filesize && " \ 760 "protect on $ubootaddr +$filesize && " \ 761 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 762 "consoledev=ttyS0\0" \ 763 "ramdiskaddr=2000000\0" \ 764 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ 765 "fdtaddr=1e00000\0" \ 766 "fdtfile=" __stringify(FDTFILE) "\0" \ 767 "bdev=sda3\0" 768 769 #define CONFIG_LINUX \ 770 "setenv bootargs root=/dev/ram rw " \ 771 "console=$consoledev,$baudrate $othbootargs;" \ 772 "setenv ramdiskaddr 0x02000000;" \ 773 "setenv fdtaddr 0x00c00000;" \ 774 "setenv loadaddr 0x1000000;" \ 775 "bootm $loadaddr $ramdiskaddr $fdtaddr" 776 777 #define CONFIG_HDBOOT \ 778 "setenv bootargs root=/dev/$bdev rw " \ 779 "console=$consoledev,$baudrate $othbootargs;" \ 780 "tftp $loadaddr $bootfile;" \ 781 "tftp $fdtaddr $fdtfile;" \ 782 "bootm $loadaddr - $fdtaddr" 783 784 #define CONFIG_NFSBOOTCOMMAND \ 785 "setenv bootargs root=/dev/nfs rw " \ 786 "nfsroot=$serverip:$rootpath " \ 787 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 788 "console=$consoledev,$baudrate $othbootargs;" \ 789 "tftp $loadaddr $bootfile;" \ 790 "tftp $fdtaddr $fdtfile;" \ 791 "bootm $loadaddr - $fdtaddr" 792 793 #define CONFIG_RAMBOOTCOMMAND \ 794 "setenv bootargs root=/dev/ram rw " \ 795 "console=$consoledev,$baudrate $othbootargs;" \ 796 "tftp $ramdiskaddr $ramdiskfile;" \ 797 "tftp $loadaddr $bootfile;" \ 798 "tftp $fdtaddr $fdtfile;" \ 799 "bootm $loadaddr $ramdiskaddr $fdtaddr" 800 801 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 802 803 #include <asm/fsl_secure_boot.h> 804 805 #endif /* __CONFIG_H */ 806