1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * am3517_crane.h - Default configuration for AM3517 CraneBoard. 4 * 5 * Author: Srinath.R <srinath@mistralsolutions.com> 6 * 7 * Based on include/configs/am3517evm.h 8 * 9 * Copyright (C) 2011 Mistral Solutions pvt Ltd 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 /* 16 * High Level Configuration Options 17 */ 18 19 #include <asm/arch/cpu.h> /* get chip and board defs */ 20 #include <asm/arch/omap.h> 21 22 /* Clock Defines */ 23 #define V_OSCK 26000000 /* Clock output from T2 */ 24 #define V_SCLK (V_OSCK >> 1) 25 26 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 27 #define CONFIG_SETUP_MEMORY_TAGS 1 28 #define CONFIG_INITRD_TAG 1 29 #define CONFIG_REVISION_TAG 1 30 31 /* 32 * Size of malloc() pool 33 */ 34 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 35 /* initial data */ 36 /* 37 * DDR related 38 */ 39 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 40 41 /* 42 * Hardware drivers 43 */ 44 45 /* 46 * NS16550 Configuration 47 */ 48 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 49 50 #define CONFIG_SYS_NS16550_SERIAL 51 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 52 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 53 54 /* 55 * select serial console configuration 56 */ 57 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 58 59 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 60 115200} 61 62 /* 63 * USB configuration 64 * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard 65 * Enable CONFIG_USB_MUSB_UDC for Device functionalities. 66 */ 67 68 #ifdef CONFIG_USB_AM35X 69 #ifdef CONFIG_USB_MUSB_UDC 70 /* USB device configuration */ 71 #define CONFIG_USB_DEVICE 1 72 #define CONFIG_USB_TTY 1 73 /* Change these to suit your needs */ 74 #define CONFIG_USBD_VENDORID 0x0451 75 #define CONFIG_USBD_PRODUCTID 0x5678 76 #define CONFIG_USBD_MANUFACTURER "Texas Instruments" 77 #define CONFIG_USBD_PRODUCT_NAME "AM3517CRANE" 78 #endif /* CONFIG_USB_MUSB_UDC */ 79 80 #endif /* CONFIG_USB_AM35X */ 81 82 #define CONFIG_SYS_I2C 83 84 /* 85 * Board NAND Info. 86 */ 87 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 88 /* to access */ 89 /* nand at CS0 */ 90 91 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 92 /* NAND devices */ 93 94 #define CONFIG_JFFS2_NAND 95 /* nand device jffs2 lives on */ 96 #define CONFIG_JFFS2_DEV "nand0" 97 /* start of jffs2 partition */ 98 #define CONFIG_JFFS2_PART_OFFSET 0x680000 99 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 100 101 /* Environment information */ 102 103 #define CONFIG_BOOTFILE "uImage" 104 105 #define CONFIG_EXTRA_ENV_SETTINGS \ 106 "loadaddr=0x82000000\0" \ 107 "console=ttyS2,115200n8\0" \ 108 "mmcdev=0\0" \ 109 "mmcargs=setenv bootargs console=${console} " \ 110 "root=/dev/mmcblk0p2 rw " \ 111 "rootfstype=ext3 rootwait\0" \ 112 "nandargs=setenv bootargs console=${console} " \ 113 "root=/dev/mtdblock4 rw " \ 114 "rootfstype=jffs2\0" \ 115 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 116 "bootscript=echo Running bootscript from mmc ...; " \ 117 "source ${loadaddr}\0" \ 118 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 119 "mmcboot=echo Booting from mmc ...; " \ 120 "run mmcargs; " \ 121 "bootm ${loadaddr}\0" \ 122 "nandboot=echo Booting from nand ...; " \ 123 "run nandargs; " \ 124 "nand read ${loadaddr} 280000 400000; " \ 125 "bootm ${loadaddr}\0" \ 126 127 #define CONFIG_BOOTCOMMAND \ 128 "mmc dev ${mmcdev}; if mmc rescan; then " \ 129 "if run loadbootscript; then " \ 130 "run bootscript; " \ 131 "else " \ 132 "if run loaduimage; then " \ 133 "run mmcboot; " \ 134 "else run nandboot; " \ 135 "fi; " \ 136 "fi; " \ 137 "else run nandboot; fi" 138 139 /* 140 * Miscellaneous configurable options 141 */ 142 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 143 #define CONFIG_SYS_MAXARGS 32 /* max number of command */ 144 /* args */ 145 /* memtest works on */ 146 147 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 148 /* address */ 149 150 /* 151 * AM3517 has 12 GP timers, they can be driven by the system clock 152 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 153 * This rate is divided by a local divisor. 154 */ 155 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 156 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 157 158 /*----------------------------------------------------------------------- 159 * Physical Memory Map 160 */ 161 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 162 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 163 164 /*----------------------------------------------------------------------- 165 * FLASH and environment organization 166 */ 167 168 /* **** PISMO SUPPORT *** */ 169 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ 170 /* on one chip */ 171 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 172 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 173 174 #define CONFIG_SYS_FLASH_BASE NAND_BASE 175 176 /* Monitor at start of flash */ 177 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 178 179 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB sector */ 180 181 /*----------------------------------------------------------------------- 182 * CFI FLASH driver setup 183 */ 184 /* timeout values are in ticks */ 185 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 186 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 187 188 /* Flash banks JFFS2 should use */ 189 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 190 CONFIG_SYS_MAX_NAND_DEVICE) 191 #define CONFIG_SYS_JFFS2_MEM_NAND 192 /* use flash_info[2] */ 193 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 194 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 195 196 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 197 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 198 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 199 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 200 CONFIG_SYS_INIT_RAM_SIZE - \ 201 GENERATED_GBL_DATA_SIZE) 202 203 /* Defines for SPL */ 204 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 205 CONFIG_SPL_TEXT_BASE) 206 207 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 208 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 209 210 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 211 212 /* NAND boot config */ 213 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 214 #define CONFIG_SYS_NAND_PAGE_COUNT 64 215 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 216 #define CONFIG_SYS_NAND_OOBSIZE 64 217 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 218 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 219 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 220 10, 11, 12, 13} 221 #define CONFIG_SYS_NAND_ECCSIZE 512 222 #define CONFIG_SYS_NAND_ECCBYTES 3 223 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 224 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 225 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 226 227 /* 228 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 229 * 64 bytes before this address should be set aside for u-boot.img's 230 * header. That is 0x800FFFC0--0x80100000 should not be used for any 231 * other needs. 232 */ 233 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 234 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 235 236 #endif /* __CONFIG_H */ 237