1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2017 Andes Technology Corporation 4 * Rick Chen, Andes Technology Corporation <rick@andestech.com> 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #ifdef CONFIG_SPL 11 #define CONFIG_SPL_MAX_SIZE 0x00100000 12 #define CONFIG_SPL_BSS_START_ADDR 0x04000000 13 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 14 15 #ifdef CONFIG_SPL_MMC_SUPPORT 16 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.itb" 17 #endif 18 #endif 19 20 #define RISCV_MMODE_TIMERBASE 0xe6000000 21 #define RISCV_MMODE_TIMER_FREQ 60000000 22 23 #define RISCV_SMODE_TIMER_FREQ 60000000 24 25 /* 26 * CPU and Board Configuration Options 27 */ 28 29 /* 30 * Miscellaneous configurable options 31 */ 32 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 33 34 /* 35 * Print Buffer Size 36 */ 37 #define CONFIG_SYS_PBSIZE \ 38 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 39 40 /* 41 * max number of command args 42 */ 43 #define CONFIG_SYS_MAXARGS 16 44 45 /* 46 * Boot Argument Buffer Size 47 */ 48 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 49 50 /* 51 * Size of malloc() pool 52 * 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough 53 */ 54 #define CONFIG_SYS_MALLOC_LEN (512 << 10) 55 56 /* DT blob (fdt) address */ 57 #define CONFIG_SYS_FDT_BASE 0x800f0000 58 59 /* 60 * Physical Memory Map 61 */ 62 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 63 #define PHYS_SDRAM_1 \ 64 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ 65 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 66 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 67 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 68 69 /* 70 * Serial console configuration 71 */ 72 #define CONFIG_SYS_NS16550_SERIAL 73 #ifndef CONFIG_DM_SERIAL 74 #define CONFIG_SYS_NS16550_REG_SIZE -4 75 #endif 76 #define CONFIG_SYS_NS16550_CLK 19660800 77 78 /* Init Stack Pointer */ 79 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000000 - \ 80 GENERATED_GBL_DATA_SIZE) 81 82 /* 83 * Load address and memory test area should agree with 84 * arch/riscv/config.mk. Be careful not to overwrite U-Boot itself. 85 */ 86 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* SDRAM */ 87 88 /* 89 * memtest works on 512 MB in DRAM 90 */ 91 92 /* 93 * FLASH and environment organization 94 */ 95 96 /* use CFI framework */ 97 98 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 99 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL 100 101 /* support JEDEC */ 102 #ifdef CONFIG_CFI_FLASH 103 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 104 #endif/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ 105 #define PHYS_FLASH_1 0x88000000 /* BANK 0 */ 106 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 107 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } 108 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 109 110 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ 111 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ 112 113 /* max number of memory banks */ 114 /* 115 * There are 4 banks supported for this Controller, 116 * but we have only 1 bank connected to flash on board 117 */ 118 #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT 119 #define CONFIG_SYS_MAX_FLASH_BANKS 1 120 #endif 121 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} 122 123 /* max number of sectors on one chip */ 124 #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) 125 #define CONFIG_SYS_MAX_FLASH_SECT 512 126 127 /* environments */ 128 129 /* SPI FLASH */ 130 131 /* 132 * For booting Linux, the board info and command line data 133 * have to be in the first 16 MB of memory, since this is 134 * the maximum mapped by the Linux kernel during initialization. 135 */ 136 137 /* Initial Memory map for Linux*/ 138 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) 139 /* Increase max gunzip size */ 140 #define CONFIG_SYS_BOOTM_LEN (64 << 20) 141 142 /* When we use RAM as ENV */ 143 144 /* Enable distro boot */ 145 #define BOOT_TARGET_DEVICES(func) \ 146 func(MMC, mmc, 0) \ 147 func(DHCP, dhcp, na) 148 #include <config_distro_bootcmd.h> 149 150 #define CONFIG_EXTRA_ENV_SETTINGS \ 151 "kernel_addr_r=0x00080000\0" \ 152 "pxefile_addr_r=0x01f00000\0" \ 153 "scriptaddr=0x01f00000\0" \ 154 "fdt_addr_r=0x02000000\0" \ 155 "ramdisk_addr_r=0x02800000\0" \ 156 BOOTENV 157 158 #endif /* __CONFIG_H */ 159