1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * brtpp1.h 4 * 5 * specific parts for B&R T-Series Motherboard 6 * 7 * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> - 8 * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com 9 */ 10 11 #ifndef __CONFIG_BRPPT1_H__ 12 #define __CONFIG_BRPPT1_H__ 13 14 #include <configs/bur_cfg_common.h> 15 #include <configs/bur_am335x_common.h> 16 #include <linux/stringify.h> 17 /* ------------------------------------------------------------------------- */ 18 /* memory */ 19 #define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) 20 #define CONFIG_SYS_BOOTM_LEN SZ_32M 21 22 /* Clock Defines */ 23 #define V_OSCK 26000000 /* Clock output from T2 */ 24 #define V_SCLK (V_OSCK) 25 26 #define CONFIG_POWER_TPS65217 27 28 /* Support both device trees and ATAGs. */ 29 #define CONFIG_CMDLINE_TAG 30 #define CONFIG_SETUP_MEMORY_TAGS 31 #define CONFIG_INITRD_TAG 32 /*#define CONFIG_MACH_TYPE 3589*/ 33 #define CONFIG_MACH_TYPE 0xFFFFFFFF /* TODO: check with kernel*/ 34 35 /* 36 * When we have NAND flash we expect to be making use of mtdparts, 37 * both for ease of use in U-Boot and for passing information on to 38 * the Linux kernel. 39 */ 40 41 #ifdef CONFIG_SPL_OS_BOOT 42 #define CONFIG_SYS_SPL_ARGS_ADDR 0x80F80000 43 44 /* RAW SD card / eMMC */ 45 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */ 46 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ 47 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ 48 49 /* NAND */ 50 #ifdef CONFIG_MTD_RAW_NAND 51 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x140000 52 #endif /* CONFIG_MTD_RAW_NAND */ 53 #endif /* CONFIG_SPL_OS_BOOT */ 54 55 #ifdef CONFIG_MTD_RAW_NAND 56 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 57 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 58 #endif /* CONFIG_MTD_RAW_NAND */ 59 60 #ifdef CONFIG_MTD_RAW_NAND 61 #define NANDTGTS \ 62 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ 63 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ 64 "cfgscr=mw ${dtbaddr} 0; nand read ${cfgaddr} cfgscr && source ${cfgaddr};" \ 65 " fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0" \ 66 "nandargs=setenv bootargs console=${console} ${optargs} ${optargs_rot} " \ 67 "root=mtd6 rootfstype=jffs2 b_mode=${b_mode}\0" \ 68 "b_nand=nand read ${loadaddr} kernel; nand read ${dtbaddr} dtb; " \ 69 "run nandargs; run cfgscr; bootz ${loadaddr} - ${dtbaddr}\0" \ 70 "b_tgts_std=usb0 nand net\0" \ 71 "b_tgts_rcy=net usb0 nand\0" \ 72 "b_tgts_pme=usb0 nand net\0" 73 #else 74 #define NANDTGTS "" 75 #endif /* CONFIG_MTD_RAW_NAND */ 76 77 #define MMCSPI_TGTS \ 78 "t30args#0=setenv bootargs ${optargs_rot} ${optargs} console=${console} " \ 79 "b_mode=${b_mode} root=/dev/mmcblk0p2 rootfstype=ext4\0" \ 80 "b_t30lgcy#0=" \ 81 "load ${loaddev}:2 ${loadaddr} /boot/PPTImage.md5 && " \ 82 "load ${loaddev}:2 ${loadaddr} /boot/zImage && " \ 83 "load ${loaddev}:2 ${dtbaddr} /boot/am335x-ppt30.dtb || " \ 84 "load ${loaddev}:1 ${dtbaddr} am335x-ppt30-legacy.dtb; "\ 85 "run t30args#0; run cfgscr; bootz ${loadaddr} - ${dtbaddr}\0" \ 86 "t30args#1=setenv bootargs ${optargs_rot} ${optargs} console=${console} " \ 87 "b_mode=${b_mode}\0" \ 88 "b_t30lgcy#1=" \ 89 "load ${loaddev}:1 ${loadaddr} zImage && " \ 90 "load ${loaddev}:1 ${dtbaddr} am335x-ppt30.dtb && " \ 91 "load ${loaddev}:1 ${ramaddr} rootfsPPT30.uboot && " \ 92 "run t30args#1; run cfgscr; bootz ${loadaddr} ${ramaddr} ${dtbaddr}\0" \ 93 "b_mmc0=load ${loaddev}:1 ${scraddr} bootscr.img && source ${scraddr}\0" \ 94 "b_mmc1=load ${loaddev}:1 ${scraddr} /boot/bootscr.img && source ${scraddr}\0" \ 95 "b_tgts_std=mmc0 mmc1 t30lgcy#0 t30lgcy#1 usb0 net\0" \ 96 "b_tgts_rcy=t30lgcy#1 usb0 net\0" \ 97 "b_tgts_pme=net usb0 mmc0 mmc1\0" \ 98 "loaddev=mmc 1\0" 99 100 #ifdef CONFIG_ENV_IS_IN_MMC 101 #define MMCTGTS \ 102 MMCSPI_TGTS \ 103 "cfgscr=mw ${dtbaddr} 0;" \ 104 " mmc dev 1; mmc read ${cfgaddr} 200 80; source ${cfgaddr};" \ 105 " fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0" 106 #else 107 #define MMCTGTS "" 108 #endif /* CONFIG_MMC */ 109 110 #ifdef CONFIG_SPI 111 #define SPITGTS \ 112 MMCSPI_TGTS \ 113 "cfgscr=mw ${dtbaddr} 0;" \ 114 " sf probe; sf read ${cfgaddr} 0xC0000 10000; source ${cfgaddr};" \ 115 " fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0" 116 #else 117 #define SPITGTS "" 118 #endif /* CONFIG_SPI */ 119 120 #define LOAD_OFFSET(x) 0x8##x 121 122 #ifndef CONFIG_SPL_BUILD 123 #define CONFIG_EXTRA_ENV_SETTINGS \ 124 BUR_COMMON_ENV \ 125 "verify=no\0" \ 126 "autoload=0\0" \ 127 "scraddr=" __stringify(LOAD_OFFSET(0000000)) "\0" \ 128 "cfgaddr=" __stringify(LOAD_OFFSET(0020000)) "\0" \ 129 "dtbaddr=" __stringify(LOAD_OFFSET(0040000)) "\0" \ 130 "loadaddr=" __stringify(LOAD_OFFSET(0100000)) "\0" \ 131 "ramaddr=" __stringify(LOAD_OFFSET(2000000)) "\0" \ 132 "console=ttyO0,115200n8\0" \ 133 "optargs=consoleblank=0 quiet panic=2\0" \ 134 "b_break=0\0" \ 135 "b_usb0=usb start && load usb 0 ${scraddr} bootscr.img && source ${scraddr}\0" \ 136 "b_net=tftp ${scraddr} netscript.img && source ${scraddr}\0" \ 137 MMCTGTS \ 138 SPITGTS \ 139 NANDTGTS \ 140 "b_deftgts=if test ${b_mode} = 12; then setenv b_tgts ${b_tgts_pme};" \ 141 " elif test ${b_mode} = 0; then setenv b_tgts ${b_tgts_rcy};" \ 142 " else setenv b_tgts ${b_tgts_std}; fi\0" \ 143 "b_default=run b_deftgts; for target in ${b_tgts};"\ 144 " do echo \"### booting ${target} ###\"; run b_${target};" \ 145 " if test ${b_break} = 1; then; exit; fi; done\0" 146 #endif /* !CONFIG_SPL_BUILD*/ 147 148 #ifdef CONFIG_MTD_RAW_NAND 149 /* 150 * GPMC block. We support 1 device and the physical address to 151 * access CS0 at is 0x8000000. 152 */ 153 #define CONFIG_SYS_MAX_NAND_DEVICE 1 154 #define CONFIG_SYS_NAND_BASE 0x8000000 155 /* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */ 156 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW 157 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 158 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 159 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 160 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ 161 CONFIG_SYS_NAND_PAGE_SIZE) 162 #define CONFIG_SYS_NAND_OOBSIZE 64 163 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 164 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, \ 165 10, 11, 12, 13, 14, 15, 16, 17, \ 166 18, 19, 20, 21, 22, 23, 24, 25, \ 167 26, 27, 28, 29, 30, 31, 32, 33, \ 168 34, 35, 36, 37, 38, 39, 40, 41, \ 169 42, 43, 44, 45, 46, 47, 48, 49, \ 170 50, 51, 52, 53, 54, 55, 56, 57, } 171 172 #define CONFIG_SYS_NAND_ECCSIZE 512 173 #define CONFIG_SYS_NAND_ECCBYTES 14 174 175 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 176 177 #define CONFIG_NAND_OMAP_GPMC_WSCFG 1 178 #endif /* CONFIG_MTD_RAW_NAND */ 179 180 #if defined(CONFIG_ENV_IS_IN_NAND) 181 #define CONFIG_SYS_ENV_SECT_SIZE CONFIG_ENV_SIZE 182 #endif 183 184 #endif /* ! __CONFIG_BRPPT1_H__ */ 185