1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2015 CompuLab, Ltd. 4 * 5 * Configuration settings for the CompuLab CL-SOM-iMX7 System-on-Module. 6 */ 7 8 #ifndef __CL_SOM_IMX7_CONFIG_H 9 #define __CL_SOM_IMX7_CONFIG_H 10 11 #include "mx7_common.h" 12 13 #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR 14 15 /* Size of malloc() pool */ 16 #define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) 17 18 /* Network */ 19 #define CONFIG_FEC_MXC 20 #define CONFIG_FEC_XCV_TYPE RGMII 21 #define CONFIG_ETHPRIME "FEC" 22 #define CONFIG_FEC_MXC_PHYADDR 0 23 24 /* ENET1 */ 25 #define IMX_FEC_BASE ENET_IPS_BASE_ADDR 26 27 /* PMIC */ 28 #define CONFIG_POWER 29 #define CONFIG_POWER_I2C 30 #define CONFIG_POWER_PFUZE3000 31 #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 32 33 /* I2C configs */ 34 #define CONFIG_SYS_I2C 35 #define CONFIG_SYS_I2C_MXC 36 #define CONFIG_SYS_I2C_MXC_I2C2 /* Enable I2C bus 2 */ 37 #define CONFIG_SYS_I2C_SPEED 100000 38 #define SYS_I2C_BUS_SOM 0 39 40 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 41 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 42 #define CONFIG_SYS_I2C_EEPROM_BUS SYS_I2C_BUS_SOM 43 44 #define CONFIG_PCA953X 45 #define CONFIG_SYS_I2C_PCA953X_ADDR 0x20 46 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} } 47 48 #undef CONFIG_SYS_AUTOLOAD 49 #undef CONFIG_EXTRA_ENV_SETTINGS 50 #undef CONFIG_BOOTCOMMAND 51 52 #define CONFIG_SYS_AUTOLOAD "no" 53 54 #define CONFIG_EXTRA_ENV_SETTINGS \ 55 "autoload=off\0" \ 56 "script=boot.scr\0" \ 57 "loadscript=load ${storagetype} ${storagedev} ${loadaddr} ${script};\0" \ 58 "loadkernel=load ${storagetype} ${storagedev} ${loadaddr} ${kernel};\0" \ 59 "loadfdt=load ${storagetype} ${storagedev} ${fdtaddr} ${fdtfile};\0" \ 60 "bootscript=echo Running bootscript from ${storagetype} ...; source ${loadaddr};\0" \ 61 "storagebootcmd=echo Booting from ${storagetype} ...; run ${storagetype}args; run doboot;\0" \ 62 "kernel=zImage\0" \ 63 "console=ttymxc0\0" \ 64 "fdt_high=0xffffffff\0" \ 65 "initrd_high=0xffffffff\0" \ 66 "fdtfile=imx7d-sbc-imx7.dtb\0" \ 67 "fdtaddr=0x83000000\0" \ 68 "mmcdev_def="__stringify(CONFIG_SYS_MMC_DEV)"\0" \ 69 "usbdev_def="__stringify(CONFIG_SYS_USB_DEV)"\0" \ 70 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ 71 "usbpart=" __stringify(CONFIG_SYS_USB_IMG_LOAD_PART) "\0" \ 72 "doboot=bootz ${loadaddr} - ${fdtaddr}\0" \ 73 "mmc_config=mmc dev ${mmcdev}; mmc rescan\0" \ 74 "mmcargs=setenv bootargs console=${console},${baudrate} " \ 75 "root=/dev/mmcblk${mmcblk}p2 rootwait rw\0" \ 76 "mmcbootscript=" \ 77 "if run mmc_config; then " \ 78 "setenv storagetype mmc;" \ 79 "setenv storagedev ${mmcdev}:${mmcpart};" \ 80 "if run loadscript; then " \ 81 "run bootscript; " \ 82 "fi; " \ 83 "fi;\0" \ 84 "mmcboot=" \ 85 "if run mmc_config; then " \ 86 "setenv storagetype mmc;" \ 87 "setenv storagedev ${mmcdev}:${mmcpart};" \ 88 "if run loadkernel; then " \ 89 "if run loadfdt; then " \ 90 "run storagebootcmd;" \ 91 "fi; " \ 92 "fi; " \ 93 "fi;\0" \ 94 "sdbootscript=setenv mmcdev ${mmcdev_def}; setenv mmcblk 0; " \ 95 "run mmcbootscript\0" \ 96 "usbbootscript=setenv usbdev ${usbdev_def}; " \ 97 "setenv storagetype usb;" \ 98 "setenv storagedev ${usbdev}:${usbpart};" \ 99 "if run loadscript; then " \ 100 "run bootscript; " \ 101 "fi; " \ 102 "sdboot=setenv mmcdev ${mmcdev_def}; setenv mmcblk 0; run mmcboot\0" \ 103 "emmcbootscript=setenv mmcdev 1; setenv mmcblk 2; run mmcbootscript\0" \ 104 "emmcboot=setenv mmcdev 1; setenv mmcblk 2; run mmcboot\0" \ 105 106 #define CONFIG_BOOTCOMMAND \ 107 "echo SD boot attempt ...; run sdbootscript; run sdboot; " \ 108 "echo eMMC boot attempt ...; run emmcbootscript; run emmcboot; " \ 109 "echo USB boot attempt ...; run usbbootscript; " 110 111 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 112 #define CONFIG_SYS_HZ 1000 113 114 /* Physical Memory Map */ 115 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR 116 117 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 118 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 119 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 120 121 #define CONFIG_SYS_INIT_SP_OFFSET \ 122 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 123 #define CONFIG_SYS_INIT_SP_ADDR \ 124 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 125 126 /* SPI Flash support */ 127 128 /* FLASH and environment organization */ 129 130 /* MMC Config*/ 131 #ifdef CONFIG_FSL_USDHC 132 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR 133 134 #define CONFIG_SYS_FSL_USDHC_NUM 2 135 #define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ 136 #endif 137 138 /* USB Configs */ 139 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 140 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 141 #define CONFIG_MXC_USB_FLAGS 0 142 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 143 144 /* SPL */ 145 #include "imx7_spl.h" 146 147 #endif /* __CONFIG_H */ 148