1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2014 Stefan Roese <sr@denx.de>
4  * Copyright (C) 2016 Mario Six <mario.six@gdsys.cc>
5  */
6 
7 #ifndef _CONFIG_CONTROLCENTERDC_H
8 #define _CONFIG_CONTROLCENTERDC_H
9 
10 /*
11  * High Level Configuration Options (easy to change)
12  */
13 #define CONFIG_CUSTOMER_BOARD_SUPPORT
14 
15 #define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
16 
17 /*
18  * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
19  * for DDR ECC byte filling in the SPL before loading the main
20  * U-Boot into it.
21  */
22 
23 #define CONFIG_SYS_TCLK		250000000	/* 250MHz */
24 
25 #define CONFIG_LOADADDR 		1000000
26 
27 /*
28  * SDIO/MMC Card Configuration
29  */
30 #define CONFIG_SYS_MMC_BASE		MVEBU_SDIO_BASE
31 
32 /*
33  * SATA/SCSI/AHCI configuration
34  */
35 #define CONFIG_SCSI_AHCI_PLAT
36 #define CONFIG_SYS_SCSI_MAX_SCSI_ID	2
37 #define CONFIG_SYS_SCSI_MAX_LUN		1
38 #define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
39 					 CONFIG_SYS_SCSI_MAX_LUN)
40 
41 /* USB/EHCI configuration */
42 #define CONFIG_EHCI_IS_TDI
43 
44 /* Environment in SPI NOR flash */
45 
46 #define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
47 
48 /* PCIe support */
49 #ifndef CONFIG_SPL_BUILD
50 #define CONFIG_PCI_SCAN_SHOW
51 #endif
52 
53 /*
54  * Software (bit-bang) MII driver configuration
55  */
56 #define CONFIG_BITBANGMII_MULTI
57 
58 /* SPL */
59 /*
60  * Select the boot device here
61  *
62  * Currently supported are:
63  * SPL_BOOT_SPI_NOR_FLASH	- Booting via SPI NOR flash
64  * SPL_BOOT_SDIO_MMC_CARD	- Booting via SDIO/MMC card (partition 1)
65  */
66 #define SPL_BOOT_SPI_NOR_FLASH		1
67 #define SPL_BOOT_SDIO_MMC_CARD		2
68 #define CONFIG_SPL_BOOT_DEVICE		SPL_BOOT_SPI_NOR_FLASH
69 
70 /* Defines for SPL */
71 #define CONFIG_SPL_SIZE			(160 << 10)
72 
73 #if defined(CONFIG_SECURED_MODE_IMAGE)
74 #define CONFIG_SPL_MAX_SIZE		(CONFIG_SPL_SIZE - 0x2614)
75 #else
76 #define CONFIG_SPL_MAX_SIZE		(CONFIG_SPL_SIZE - 0x30)
77 #endif
78 
79 #define CONFIG_SPL_BSS_START_ADDR	(0x40000000 + CONFIG_SPL_SIZE)
80 #define CONFIG_SPL_BSS_MAX_SIZE		(16 << 10)
81 
82 #ifdef CONFIG_SPL_BUILD
83 #define CONFIG_SYS_MALLOC_SIMPLE
84 #endif
85 
86 #define CONFIG_SPL_STACK		(0x40000000 + ((212 - 16) << 10))
87 #define CONFIG_SPL_BOOTROM_SAVE		(CONFIG_SPL_STACK + 4)
88 
89 #define CONFIG_SPL_LIBCOMMON_SUPPORT
90 #define CONFIG_SPL_LIBGENERIC_SUPPORT
91 #define CONFIG_SPL_I2C_SUPPORT
92 
93 #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
94 /* SPL related SPI defines */
95 #define CONFIG_SYS_U_BOOT_OFFS		CONFIG_SYS_SPI_U_BOOT_OFFS
96 #endif
97 
98 #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
99 /* SPL related MMC defines */
100 #define CONFIG_SPL_MMC_SUPPORT
101 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
102 #define CONFIG_SYS_MMC_U_BOOT_OFFS		(168 << 10)
103 #define CONFIG_SYS_U_BOOT_OFFS			CONFIG_SYS_MMC_U_BOOT_OFFS
104 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	(CONFIG_SYS_U_BOOT_OFFS / 512)
105 #ifdef CONFIG_SPL_BUILD
106 #define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER	0x00180000	/* in SDRAM */
107 #endif
108 #endif
109 
110 /*
111  * Environment Configuration
112  */
113 
114 #define CONFIG_HOSTNAME		"ccdc"
115 #define CONFIG_ROOTPATH		"/opt/nfsroot"
116 #define CONFIG_BOOTFILE		"ccdc.img"
117 
118 #define CONFIG_EXTRA_ENV_SETTINGS						\
119 	"netdev=eth1\0"						\
120 	"consoledev=ttyS1\0"							\
121 	"u-boot=u-boot.bin\0"							\
122 	"bootfile_addr=1000000\0"						\
123 	"keyprogram_addr=3000000\0"						\
124 	"keyprogram_file=keyprogram.img\0"						\
125 	"fdtfile=controlcenterdc.dtb\0"						\
126 	"load=tftpboot ${loadaddr} ${u-boot}\0"					\
127 	"mmcdev=0:2\0"								\
128 	"update=sf probe 1:0;"							\
129 		" sf erase 0 +${filesize};"					\
130 		" sf write ${fileaddr} 0 ${filesize}\0"				\
131 	"upd=run load update\0"							\
132 	"fdt_high=0x10000000\0"							\
133 	"initrd_high=0x10000000\0"						\
134 	"loadkeyprogram=tpm flush_keys;"					\
135 		" mmc rescan;"							\
136 		" ext4load mmc ${mmcdev} ${keyprogram_addr} ${keyprogram_file};"\
137 		" source ${keyprogram_addr}:script@1\0"				\
138 	"gpio1=gpio@22_25\0"							\
139 	"gpio2=A29\0"								\
140 	"blinkseq='0 0 0 0 2 0 2 2 3 1 3 1 0 0 2 2 3 1 3 3 2 0 2 2 3 1 1 1 "	\
141 		  "2 0 2 2 3 1 3 1 0 0 2 0 3 3 3 1 2 0 0 0 3 1 1 1 0 0 0 0'\0"	\
142 	"bootfail=for i in ${blinkseq}; do"					\
143 		" if test $i -eq 0; then"					\
144 		" gpio clear ${gpio1}; gpio set ${gpio2};"			\
145 		" elif test $i -eq 1; then"					\
146 		" gpio clear ${gpio1}; gpio clear ${gpio2};"			\
147 		" elif test $i -eq 2; then"					\
148 		" gpio set ${gpio1}; gpio set ${gpio2};"			\
149 		" else;"							\
150 		" gpio clear ${gpio1}; gpio set ${gpio2};"			\
151 		" fi; sleep 0.12; done\0"
152 
153 #define CONFIG_NFSBOOTCOMMAND								\
154 	"setenv bootargs root=/dev/nfs rw "						\
155 	"nfsroot=${serverip}:${rootpath} "						\
156 	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off "	\
157 	"console=${consoledev},${baudrate} ${othbootargs}; "				\
158 	"tftpboot ${bootfile_addr} ${bootfile}; "						\
159 	"bootm ${bootfile_addr}"
160 
161 #define CONFIG_MMCBOOTCOMMAND					\
162 	"setenv bootargs root=/dev/mmcblk0p3 rw rootwait "	\
163 	"console=${consoledev},${baudrate} ${othbootargs}; "	\
164 	"ext2load mmc 0:2 ${bootfile_addr} ${bootfile}; "	\
165 	"bootm ${bootfile_addr}"
166 
167 #define CONFIG_BOOTCOMMAND			\
168 	"if env exists keyprogram; then;"	\
169 	" setenv keyprogram; run nfsboot;"	\
170         " fi;"					\
171         " run dobootfail"
172 
173 /*
174  * mv-common.h should be defined after CMD configs since it used them
175  * to enable certain macros
176  */
177 #include "mv-common.h"
178 
179 #endif /* _CONFIG_CONTROLCENTERDC_H */
180