1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 4 * 5 * Based on davinci_dvevm.h. Original Copyrights follow: 6 * 7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 /* 14 * Board 15 */ 16 17 /* 18 * SoC Configuration 19 */ 20 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH 21 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) 22 #define CONFIG_SYS_OSCIN_FREQ 24000000 23 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE 24 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) 25 #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY 26 27 #ifdef CONFIG_MTD_NOR_FLASH 28 #define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) 29 #endif 30 31 /* 32 * Memory Info 33 */ 34 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ 35 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ 36 #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ 37 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ 38 #define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE 39 #define CONFIG_SPL_BSS_MAX_SIZE 0x1080000 40 /* memtest start addr */ 41 42 /* memtest will be run on 16MB */ 43 44 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ 45 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ 46 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ 47 DAVINCI_SYSCFG_SUSPSRC_UART2 | \ 48 DAVINCI_SYSCFG_SUSPSRC_EMAC | \ 49 DAVINCI_SYSCFG_SUSPSRC_I2C) 50 51 /* 52 * PLL configuration 53 */ 54 55 #define CONFIG_SYS_DA850_PLL0_PLLM 24 56 #define CONFIG_SYS_DA850_PLL1_PLLM 21 57 58 /* 59 * DDR2 memory configuration 60 */ 61 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ 62 DV_DDR_PHY_EXT_STRBEN | \ 63 (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT)) 64 65 #define CONFIG_SYS_DA850_DDR2_SDBCR ( \ 66 (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \ 67 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ 68 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ 69 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ 70 (0x3 << DV_DDR_SDCR_CL_SHIFT) | \ 71 (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \ 72 (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) 73 74 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ 75 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0 76 77 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ 78 (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \ 79 (2 << DV_DDR_SDTMR1_RP_SHIFT) | \ 80 (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \ 81 (1 << DV_DDR_SDTMR1_WR_SHIFT) | \ 82 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ 83 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ 84 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ 85 (0 << DV_DDR_SDTMR1_WTR_SHIFT)) 86 87 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ 88 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ 89 (0 << DV_DDR_SDTMR2_XP_SHIFT) | \ 90 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ 91 (17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ 92 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ 93 (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \ 94 (0 << DV_DDR_SDTMR2_CKE_SHIFT)) 95 96 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494 97 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 98 99 /* 100 * Serial Driver info 101 */ 102 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) 103 104 #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) 105 106 /* 107 * I2C Configuration 108 */ 109 #ifndef CONFIG_SPL_BUILD 110 #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 111 #endif 112 113 /* 114 * Flash & Environment 115 */ 116 #ifdef CONFIG_MTD_RAW_NAND 117 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST 118 #define CONFIG_SYS_NAND_PAGE_2K 119 #define CONFIG_SYS_NAND_CS 3 120 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 121 #define CONFIG_SYS_NAND_MASK_CLE 0x10 122 #define CONFIG_SYS_NAND_MASK_ALE 0x8 123 #undef CONFIG_SYS_NAND_HW_ECC 124 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ 125 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST 126 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 127 #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) 128 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) 129 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000 130 #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 131 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 132 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ 133 CONFIG_SYS_NAND_U_BOOT_SIZE - \ 134 CONFIG_SYS_MALLOC_LEN - \ 135 GENERATED_GBL_DATA_SIZE) 136 #define CONFIG_SYS_NAND_ECCPOS { \ 137 24, 25, 26, 27, 28, \ 138 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \ 139 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \ 140 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \ 141 59, 60, 61, 62, 63 } 142 #define CONFIG_SYS_NAND_PAGE_COUNT 64 143 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 144 #define CONFIG_SYS_NAND_ECCSIZE 512 145 #define CONFIG_SYS_NAND_ECCBYTES 10 146 #define CONFIG_SYS_NAND_OOBSIZE 64 147 #define CONFIG_SPL_NAND_LOAD 148 149 #ifndef CONFIG_SPL_BUILD 150 #define CONFIG_SYS_NAND_SELF_INIT 151 #endif 152 #endif 153 154 /* 155 * Network & Ethernet Configuration 156 */ 157 #ifdef CONFIG_DRIVER_TI_EMAC 158 #define CONFIG_NET_RETRY_COUNT 10 159 #endif 160 161 #ifdef CONFIG_MTD_NOR_FLASH 162 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ 163 #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ 164 #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 165 #define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */ 166 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\ 167 + 3) 168 #endif 169 170 /* 171 * U-Boot general configuration 172 */ 173 #define CONFIG_BOOTFILE "uImage" /* Boot file name */ 174 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 175 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ 176 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) 177 178 /* 179 * Linux Information 180 */ 181 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) 182 #define CONFIG_HWCONFIG /* enable hwconfig */ 183 #define CONFIG_CMDLINE_TAG 184 #define CONFIG_REVISION_TAG 185 #define CONFIG_SETUP_MEMORY_TAGS 186 187 #define CONFIG_BOOTCOMMAND \ 188 "run envboot; " \ 189 "run mmcboot; " 190 191 #define DEFAULT_LINUX_BOOT_ENV \ 192 "loadaddr=0xc0700000\0" \ 193 "fdtaddr=0xc0600000\0" \ 194 "scriptaddr=0xc0600000\0" 195 196 #include <environment/ti/mmc.h> 197 198 #define CONFIG_EXTRA_ENV_SETTINGS \ 199 DEFAULT_LINUX_BOOT_ENV \ 200 DEFAULT_MMC_TI_ARGS \ 201 "bootpart=0:2\0" \ 202 "bootdir=/boot\0" \ 203 "bootfile=zImage\0" \ 204 "fdtfile=da850-evm.dtb\0" \ 205 "boot_fdt=yes\0" \ 206 "boot_fit=0\0" \ 207 "console=ttyS2,115200n8\0" \ 208 "hwconfig=dsp:wake=yes" 209 210 #ifdef CONFIG_CMD_BDI 211 #define CONFIG_CLOCKS 212 #endif 213 214 /* USB Configs */ 215 #define CONFIG_USB_OHCI_NEW 216 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 217 218 #ifndef CONFIG_MTD_NOR_FLASH 219 #define CONFIG_SPL_PAD_TO 32768 220 #endif 221 222 #ifdef CONFIG_SPL_BUILD 223 /* defines for SPL */ 224 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ 225 CONFIG_SYS_MALLOC_LEN) 226 #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN 227 #define CONFIG_SPL_STACK 0x8001ff00 228 #define CONFIG_SPL_MAX_FOOTPRINT 32768 229 230 #endif 231 232 /* Load U-Boot Image From MMC */ 233 234 /* additions for new relocation code, must added to all boards */ 235 #define CONFIG_SYS_SDRAM_BASE 0xc0000000 236 237 #ifdef CONFIG_MTD_NOR_FLASH 238 #define CONFIG_SYS_INIT_SP_ADDR 0x8001ff00 239 #else 240 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ 241 GENERATED_GBL_DATA_SIZE) 242 #endif /* CONFIG_MTD_NOR_FLASH */ 243 244 #include <asm/arch/hardware.h> 245 246 #endif /* __CONFIG_H */ 247