1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2013 4 * Texas Instruments Incorporated. 5 * Lokesh Vutla <lokeshvutla@ti.com> 6 * 7 * Configuration settings for the TI DRA7XX board. 8 * See ti_omap5_common.h for omap5 common settings. 9 */ 10 11 #ifndef __CONFIG_DRA7XX_EVM_H 12 #define __CONFIG_DRA7XX_EVM_H 13 14 #include <environment/ti/dfu.h> 15 16 #define CONFIG_IODELAY_RECALIBRATION 17 18 #define CONFIG_VERY_BIG_RAM 19 #define CONFIG_MAX_MEM_MAPPED 0x80000000 20 21 #ifndef CONFIG_QSPI_BOOT 22 /* MMC ENV related defines */ 23 #endif 24 25 #if (CONFIG_CONS_INDEX == 1) 26 #define CONSOLEDEV "ttyS0" 27 #elif (CONFIG_CONS_INDEX == 3) 28 #define CONSOLEDEV "ttyS2" 29 #endif 30 #define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ 31 #define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ 32 #define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ 33 34 #define CONFIG_ENV_EEPROM_IS_ON_I2C 35 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ 36 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 37 38 #define CONFIG_SYS_OMAP_ABE_SYSCK 39 40 #ifndef CONFIG_SPL_BUILD 41 #define DFUARGS \ 42 "dfu_bufsiz=0x10000\0" \ 43 DFU_ALT_INFO_MMC \ 44 DFU_ALT_INFO_EMMC \ 45 DFU_ALT_INFO_RAM \ 46 DFU_ALT_INFO_QSPI 47 #endif 48 49 #ifdef CONFIG_SPL_BUILD 50 #ifdef CONFIG_SPL_DFU 51 #define DFUARGS \ 52 "dfu_bufsiz=0x10000\0" \ 53 DFU_ALT_INFO_RAM 54 #endif 55 #endif 56 57 #include <configs/ti_omap5_common.h> 58 59 /* Enhance our eMMC support / experience. */ 60 #define CONFIG_HSMMC2_8BIT 61 62 /* CPSW Ethernet */ 63 #define CONFIG_NET_RETRY_COUNT 10 64 65 /* 66 * Default to using SPI for environment, etc. 67 * 0x000000 - 0x040000 : QSPI.SPL (256KiB) 68 * 0x040000 - 0x140000 : QSPI.u-boot (1MiB) 69 * 0x140000 - 0x1C0000 : QSPI.u-boot-spl-os (512KiB) 70 * 0x1C0000 - 0x1D0000 : QSPI.u-boot-env (64KiB) 71 * 0x1D0000 - 0x1E0000 : QSPI.u-boot-env.backup1 (64KiB) 72 * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB) 73 * 0x9E0000 - 0x2000000 : USERLAND 74 */ 75 #define CONFIG_SYS_SPI_KERNEL_OFFS 0x1E0000 76 #define CONFIG_SYS_SPI_ARGS_OFFS 0x140000 77 #define CONFIG_SYS_SPI_ARGS_SIZE 0x80000 78 79 /* SPI SPL */ 80 81 /* USB xHCI HOST */ 82 #define CONFIG_USB_XHCI_OMAP 83 84 #define CONFIG_OMAP_USB2PHY2_HOST 85 86 /* SATA */ 87 #define CONFIG_SCSI_AHCI_PLAT 88 89 /* NAND support */ 90 #ifdef CONFIG_MTD_RAW_NAND 91 /* NAND: device related configs */ 92 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 93 #define CONFIG_SYS_NAND_OOBSIZE 64 94 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 95 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ 96 CONFIG_SYS_NAND_PAGE_SIZE) 97 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 98 /* NAND: driver related configs */ 99 #define CONFIG_SYS_NAND_ONFI_DETECTION 100 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW 101 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 102 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 103 10, 11, 12, 13, 14, 15, 16, 17, \ 104 18, 19, 20, 21, 22, 23, 24, 25, \ 105 26, 27, 28, 29, 30, 31, 32, 33, \ 106 34, 35, 36, 37, 38, 39, 40, 41, \ 107 42, 43, 44, 45, 46, 47, 48, 49, \ 108 50, 51, 52, 53, 54, 55, 56, 57, } 109 #define CONFIG_SYS_NAND_ECCSIZE 512 110 #define CONFIG_SYS_NAND_ECCBYTES 14 111 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00140000 112 /* NAND: SPL related configs */ 113 /* NAND: SPL falcon mode configs */ 114 #ifdef CONFIG_SPL_OS_BOOT 115 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */ 116 #endif 117 #endif /* !CONFIG_MTD_RAW_NAND */ 118 119 /* Parallel NOR Support */ 120 #if defined(CONFIG_NOR) 121 /* NOR: device related configs */ 122 #define CONFIG_SYS_MAX_FLASH_SECT 512 123 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 124 #define CONFIG_SYS_FLASH_SIZE (64 * 1024 * 1024) /* 64 MB */ 125 /* #define CONFIG_INIT_IGNORE_ERROR */ 126 #define CONFIG_SYS_MAX_FLASH_BANKS 1 127 #define CONFIG_SYS_FLASH_BASE (0x08000000) 128 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 129 /* Reduce SPL size by removing unlikey targets */ 130 #endif /* NOR support */ 131 132 #endif /* __CONFIG_DRA7XX_EVM_H */ 133