1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2012 Atmel Corporation 4 * Copyright (C) 2019 Stefan Roese <sr@denx.de> 5 * 6 * Configuation settings for the GARDENA smart Gateway (AT91SAM9G25) 7 */ 8 9 #ifndef __CONFIG_H__ 10 #define __CONFIG_H__ 11 12 #ifndef __ASSEMBLY__ 13 #include <linux/bitops.h> 14 #endif 15 16 /* ARM asynchronous clock */ 17 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 18 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ 19 20 #ifndef CONFIG_SPL_BUILD 21 #define CONFIG_SKIP_LOWLEVEL_INIT 22 #endif 23 #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY 24 25 /* general purpose I/O */ 26 #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ 27 28 /* SDRAM */ 29 #define CONFIG_SYS_SDRAM_BASE 0x20000000 30 #define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */ 31 32 #define CONFIG_SYS_INIT_SP_ADDR \ 33 (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) 34 35 #define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) 36 37 /* NAND flash */ 38 #define CONFIG_SYS_MAX_NAND_DEVICE 1 39 #define CONFIG_SYS_NAND_BASE 0x40000000 40 #define CONFIG_SYS_NAND_DBW_8 1 41 /* our ALE is AD21 */ 42 #define CONFIG_SYS_NAND_MASK_ALE BIT(21) 43 /* our CLE is AD22 */ 44 #define CONFIG_SYS_NAND_MASK_CLE BIT(22) 45 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 46 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 47 48 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 49 50 /* SPL */ 51 #define CONFIG_SPL_MAX_SIZE 0x7000 52 #define CONFIG_SPL_STACK 0x308000 53 54 #define CONFIG_SPL_BSS_START_ADDR 0x20000000 55 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 56 #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 57 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 58 59 #define CONFIG_SYS_MONITOR_LEN (512 << 10) 60 61 #define CONFIG_SYS_MASTER_CLOCK 132096000 62 #define CONFIG_SYS_AT91_PLLA 0x20c73f03 63 #define CONFIG_SYS_MCKR 0x1301 64 #define CONFIG_SYS_MCKR_CSS 0x1302 65 66 #define CONFIG_SPL_NAND_RAW_ONLY 67 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 68 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa0000 69 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 70 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 71 72 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 73 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 74 #define CONFIG_SYS_NAND_PAGE_COUNT 64 75 #define CONFIG_SYS_NAND_OOBSIZE 64 76 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 77 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 78 79 #define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS 80 #define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO 81 82 #endif 83