1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2018 Stefan Roese <sr@denx.de> 4 */ 5 6 #ifndef __CONFIG_GARDENA_SMART_GATEWAY_H 7 #define __CONFIG_GARDENA_SMART_GATEWAY_H 8 9 /* CPU */ 10 #define CONFIG_SYS_MIPS_TIMER_FREQ 290000000 11 12 /* RAM */ 13 #define CONFIG_SYS_SDRAM_BASE 0x80000000 14 15 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 16 17 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 18 19 /* SPL */ 20 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) 21 #define CONFIG_SKIP_LOWLEVEL_INIT 22 #endif 23 24 #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE 25 #define CONFIG_SPL_BSS_START_ADDR 0x80010000 26 #define CONFIG_SPL_BSS_MAX_SIZE 0x10000 27 #define CONFIG_SPL_MAX_SIZE 0x10000 28 #define CONFIG_SPL_PAD_TO 0 29 30 /* Dummy value */ 31 #define CONFIG_SYS_UBOOT_BASE 0 32 33 /* Serial SPL */ 34 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT) 35 #define CONFIG_SYS_NS16550_MEM32 36 #define CONFIG_SYS_NS16550_CLK 40000000 37 #define CONFIG_SYS_NS16550_REG_SIZE -4 38 #define CONFIG_SYS_NS16550_COM1 0xb0000c00 39 #endif 40 41 /* UART */ 42 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 43 230400, 460800, 921600 } 44 45 /* RAM */ 46 47 /* Memory usage */ 48 #define CONFIG_SYS_MAXARGS 64 49 #define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) 50 #define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) 51 #define CONFIG_SYS_CBSIZE 512 52 53 /* U-Boot */ 54 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 55 56 /* Environment settings */ 57 58 /* 59 * Environment is right behind U-Boot in flash. Make sure U-Boot 60 * doesn't grow into the environment area. 61 */ 62 #define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET 63 64 #endif /* __CONFIG_GARDENA_SMART_GATEWAY_H */ 65