1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Configuration settings for the Renesas GRPEACH board
4  *
5  * Copyright (C) 2017-2019 Renesas Electronics
6  */
7 
8 #ifndef __GRPEACH_H
9 #define __GRPEACH_H
10 
11 /* Board Clock , P1 clock frequency (XTAL=13.33MHz) */
12 #define CONFIG_SYS_CLK_FREQ	66666666
13 
14 /* Miscellaneous */
15 #define CONFIG_SYS_PBSIZE	256
16 #define CONFIG_CMDLINE_TAG
17 
18 /* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */
19 #define CONFIG_SYS_SDRAM_BASE		0x20000000
20 #define CONFIG_SYS_SDRAM_SIZE		(10 * 1024 * 1024)
21 #define CONFIG_SYS_INIT_SP_ADDR		\
22 	(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 1024 * 1024)
23 #define CONFIG_SYS_LOAD_ADDR		\
24 	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
25 
26 /* Malloc */
27 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
28 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
29 
30 /* Network interface */
31 #define CONFIG_SH_ETHER_USE_PORT	0
32 #define CONFIG_SH_ETHER_PHY_ADDR	0
33 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
34 #define CONFIG_SH_ETHER_CACHE_WRITEBACK
35 #define CONFIG_SH_ETHER_CACHE_INVALIDATE
36 #define CONFIG_SH_ETHER_ALIGNE_SIZE	64
37 #define CONFIG_BITBANGMII_MULTI
38 
39 #endif	/* __GRPEACH_H */
40