1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2010-2011 Calxeda, Inc.
4  */
5 
6 #ifndef __CONFIG_H
7 #define __CONFIG_H
8 
9 #define CONFIG_SYS_BOOTMAPSZ		(16 << 20)
10 
11 #define CONFIG_SYS_TIMER_RATE		(150000000/256)
12 #define CONFIG_SYS_TIMER_COUNTER	(0xFFF34000 + 0x4)
13 #define CONFIG_SYS_TIMER_COUNTS_DOWN
14 
15 /*
16  * Size of malloc() pool
17  */
18 #define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
19 
20 #define CONFIG_PL011_CLOCK		150000000
21 #define CONFIG_PL01x_PORTS		{ (void *)(0xFFF36000) }
22 
23 #define CONFIG_SYS_BOOTCOUNT_LE		/* Use little-endian accessors */
24 
25 #define CONFIG_SCSI_AHCI_PLAT
26 #define CONFIG_SYS_SCSI_MAX_SCSI_ID	5
27 #define CONFIG_SYS_SCSI_MAX_LUN		1
28 #define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
29 					CONFIG_SYS_SCSI_MAX_LUN)
30 
31 #define CONFIG_CALXEDA_XGMAC
32 
33 #define CONFIG_BOOT_RETRY_TIME		-1
34 #define CONFIG_RESET_TO_RETRY
35 
36 /*
37  * Miscellaneous configurable options
38  */
39 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
40 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
41 
42 #define CONFIG_SYS_LOAD_ADDR		0x800000
43 #define CONFIG_SYS_64BIT_LBA
44 
45 /*-----------------------------------------------------------------------
46  * Physical Memory Map
47  * The DRAM is already setup, so do not touch the DT node later.
48  */
49 #define PHYS_SDRAM_1_SIZE		(4089 << 20)
50 
51 /* Environment data setup
52 */
53 #define CONFIG_SYS_NVRAM_BASE_ADDR	0xfff88000	/* NVRAM base address */
54 #define CONFIG_SYS_NVRAM_SIZE		0x8000		/* NVRAM size */
55 
56 #define CONFIG_SYS_SDRAM_BASE		0x00000000
57 #define CONFIG_SYS_INIT_SP_ADDR		0x01000000
58 #define CONFIG_SKIP_LOWLEVEL_INIT
59 
60 #endif
61