1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2020 Synopsys, Inc. All rights reserved. 4 * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> 5 */ 6 7 #ifndef _CONFIG_HSDK_H_ 8 #define _CONFIG_HSDK_H_ 9 10 #include <linux/sizes.h> 11 12 /* 13 * CPU configuration 14 */ 15 #define NR_CPUS 4 16 #define ARC_PERIPHERAL_BASE 0xF0000000 17 #define ARC_DWMMC_BASE (ARC_PERIPHERAL_BASE + 0xA000) 18 #define ARC_DWGMAC_BASE (ARC_PERIPHERAL_BASE + 0x18000) 19 20 /* 21 * Memory configuration 22 */ 23 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 24 25 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 26 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 27 #define CONFIG_SYS_SDRAM_SIZE SZ_1G 28 29 #define CONFIG_SYS_INIT_SP_ADDR \ 30 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) 31 32 #define CONFIG_SYS_MALLOC_LEN SZ_2M 33 #define CONFIG_SYS_BOOTM_LEN SZ_128M 34 #define CONFIG_SYS_LOAD_ADDR 0x82000000 35 36 /* 37 * UART configuration 38 */ 39 #define CONFIG_SYS_NS16550_SERIAL 40 #define CONFIG_SYS_NS16550_CLK 33330000 41 #define CONFIG_SYS_NS16550_MEM32 42 43 /* 44 * Ethernet PHY configuration 45 */ 46 47 /* 48 * USB 1.1 configuration 49 */ 50 #define CONFIG_USB_OHCI_NEW 51 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 52 53 /* 54 * Environment settings 55 */ 56 #define CONFIG_EXTRA_ENV_SETTINGS \ 57 "upgrade=if mmc rescan && " \ 58 "fatload mmc 0:1 ${loadaddr} u-boot-update.scr && " \ 59 "iminfo ${loadaddr} && source ${loadaddr}; then; else echo " \ 60 "\"Fail to upgrade.\n" \ 61 "Do you have u-boot-update.scr and u-boot.head on first (FAT) SD card partition?\"" \ 62 "; fi\0" \ 63 "core_mask=0xF\0" \ 64 "hsdk_hs45d=setenv core_mask 0x2; setenv haps_apb_location 0x1; \ 65 setenv l2_cache_ena 0x0; setenv icache_ena 0x0; setenv csm_location 0x10; \ 66 setenv dcache_ena 0x0; setenv core_iccm_1 0x7; \ 67 setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \ 68 "hsdk_hs47d=setenv core_mask 0x1; setenv haps_apb_location 0x1; \ 69 setenv l2_cache_ena 0x0; setenv icache_ena 0x1; setenv csm_location 0x10; \ 70 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \ 71 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF;\0" \ 72 "hsdk_hs47d_ccm=setenv core_mask 0x2; setenv haps_apb_location 0x1; \ 73 setenv l2_cache_ena 0x0; setenv icache_ena 0x1; setenv csm_location 0x10; \ 74 setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \ 75 setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \ 76 "hsdk_hs48=setenv core_mask 0x1; setenv haps_apb_location 0x1; \ 77 setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \ 78 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \ 79 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF;\0" \ 80 "hsdk_hs48_ccm=setenv core_mask 0x2; setenv haps_apb_location 0x1; \ 81 setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \ 82 setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \ 83 setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \ 84 "hsdk_hs48x2=run hsdk_hs47dx2;\0" \ 85 "hsdk_hs47dx2=setenv core_mask 0x3; setenv haps_apb_location 0x1; \ 86 setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \ 87 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \ 88 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF; \ 89 setenv core_iccm_1 0x6; setenv core_dccm_1 0x6;\0" \ 90 "hsdk_hs48x3=run hsdk_hs47dx3;\0" \ 91 "hsdk_hs47dx3=setenv core_mask 0x7; setenv haps_apb_location 0x1; \ 92 setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \ 93 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \ 94 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF; \ 95 setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \ 96 setenv core_iccm_2 0x10; setenv core_dccm_2 0x10;\0" \ 97 "hsdk_hs48x4=run hsdk_hs47dx4;\0" \ 98 "hsdk_hs47dx4=setenv core_mask 0xF; setenv haps_apb_location 0x1; \ 99 setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \ 100 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \ 101 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF; \ 102 setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \ 103 setenv core_iccm_2 0x10; setenv core_dccm_2 0x10; \ 104 setenv core_iccm_3 0x6; setenv core_dccm_3 0x6;\0" 105 106 /* 107 * Environment configuration 108 */ 109 #define CONFIG_BOOTFILE "uImage" 110 #define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR 111 112 /* Cli configuration */ 113 #define CONFIG_SYS_CBSIZE SZ_2K 114 115 /* 116 * Callback configuration 117 */ 118 119 #endif /* _CONFIG_HSDK_H_ */ 120