1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2019 NXP
4  */
5 
6 #ifndef __IMX8MP_EVK_H
7 #define __IMX8MP_EVK_H
8 
9 #include <linux/sizes.h>
10 #include <linux/stringify.h>
11 #include <asm/arch/imx-regs.h>
12 
13 #define CONFIG_SYS_BOOTM_LEN		(32 * SZ_1M)
14 
15 #define CONFIG_SPL_MAX_SIZE		(152 * 1024)
16 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
17 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
18 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300
19 #define CONFIG_SYS_UBOOT_BASE	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
20 
21 #ifdef CONFIG_SPL_BUILD
22 /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
23 #define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
24 #define CONFIG_SPL_STACK		0x960000
25 #define CONFIG_SPL_BSS_START_ADDR	0x0098FC00
26 #define CONFIG_SPL_BSS_MAX_SIZE		0x400	/* 1 KB */
27 #define CONFIG_SYS_SPL_MALLOC_START	0x42200000
28 #define CONFIG_SYS_SPL_MALLOC_SIZE	SZ_512K	/* 512 KB */
29 
30 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
31 
32 #undef CONFIG_DM_MMC
33 #undef CONFIG_DM_PMIC
34 #undef CONFIG_DM_PMIC_PFUZE100
35 
36 #define CONFIG_POWER
37 #define CONFIG_POWER_I2C
38 #define CONFIG_POWER_PCA9450
39 
40 #define CONFIG_SYS_I2C
41 
42 #endif
43 
44 #if defined(CONFIG_CMD_NET)
45 #define CONFIG_ETHPRIME                 "eth1" /* Set eqos to primary since we use its MDIO */
46 
47 #define CONFIG_FEC_XCV_TYPE             RGMII
48 #define CONFIG_FEC_MXC_PHYADDR          1
49 #define FEC_QUIRK_ENET_MAC
50 
51 #define DWC_NET_PHYADDR			1
52 #ifdef CONFIG_DWC_ETH_QOS
53 #define CONFIG_SYS_NONCACHED_MEMORY     (1 * SZ_1M)     /* 1M */
54 #endif
55 
56 #define PHY_ANEG_TIMEOUT 20000
57 
58 #endif
59 
60 #ifndef CONFIG_SPL_BUILD
61 #define BOOT_TARGET_DEVICES(func) \
62        func(MMC, mmc, 1) \
63        func(MMC, mmc, 2)
64 
65 #include <config_distro_bootcmd.h>
66 #endif
67 
68 /* Initial environment variables */
69 #define CONFIG_EXTRA_ENV_SETTINGS		\
70 	BOOTENV \
71 	"scriptaddr=0x43500000\0" \
72 	"kernel_addr_r=0x40880000\0" \
73 	"image=Image\0" \
74 	"console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
75 	"fdt_addr=0x43000000\0"			\
76 	"boot_fdt=try\0" \
77 	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
78 	"initrd_addr=0x43800000\0"		\
79 	"bootm_size=0x10000000\0" \
80 	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
81 	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
82 
83 /* Link Definitions */
84 #define CONFIG_LOADADDR			0x40480000
85 
86 #define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
87 
88 #define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
89 #define CONFIG_SYS_INIT_RAM_SIZE	0x80000
90 #define CONFIG_SYS_INIT_SP_OFFSET \
91 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
92 #define CONFIG_SYS_INIT_SP_ADDR \
93 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
94 
95 #define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
96 
97 /* Size of malloc() pool */
98 #define CONFIG_SYS_MALLOC_LEN		SZ_32M
99 
100 /* Totally 6GB DDR */
101 #define CONFIG_SYS_SDRAM_BASE		0x40000000
102 #define PHYS_SDRAM			0x40000000
103 #define PHYS_SDRAM_SIZE			0xC0000000	/* 3 GB */
104 #define PHYS_SDRAM_2			0x100000000
105 #define PHYS_SDRAM_2_SIZE		0xC0000000	/* 3 GB */
106 
107 #define CONFIG_MXC_UART_BASE		UART2_BASE_ADDR
108 
109 /* Monitor Command Prompt */
110 #define CONFIG_SYS_CBSIZE		2048
111 #define CONFIG_SYS_MAXARGS		64
112 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
113 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
114 					sizeof(CONFIG_SYS_PROMPT) + 16)
115 
116 #define CONFIG_FSL_USDHC
117 
118 #define CONFIG_SYS_FSL_USDHC_NUM	2
119 #define CONFIG_SYS_FSL_ESDHC_ADDR	0
120 
121 #define CONFIG_SYS_MMC_IMG_LOAD_PART	1
122 
123 #define CONFIG_SYS_I2C_SPEED		100000
124 
125 #endif
126