1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2018 NXP 4 */ 5 6 #ifndef __IMX8M_EVK_H 7 #define __IMX8M_EVK_H 8 9 #include <linux/sizes.h> 10 #include <linux/stringify.h> 11 #include <asm/arch/imx-regs.h> 12 13 #define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) 14 15 #define CONFIG_SPL_MAX_SIZE (124 * 1024) 16 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 17 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR 18 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 19 20 #ifdef CONFIG_SPL_BUILD 21 /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ 22 #define CONFIG_SPL_WATCHDOG_SUPPORT 23 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 24 #define CONFIG_SPL_POWER_SUPPORT 25 #define CONFIG_SPL_I2C_SUPPORT 26 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 27 #define CONFIG_SPL_STACK 0x187FF0 28 #define CONFIG_SPL_LIBCOMMON_SUPPORT 29 #define CONFIG_SPL_LIBGENERIC_SUPPORT 30 #define CONFIG_SPL_GPIO_SUPPORT 31 #define CONFIG_SPL_MMC_SUPPORT 32 #define CONFIG_SPL_BSS_START_ADDR 0x00180000 33 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ 34 #define CONFIG_SYS_SPL_MALLOC_START 0x42200000 35 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ 36 #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 37 38 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ 39 #define CONFIG_MALLOC_F_ADDR 0x182000 40 /* For RAW image gives a error info not panic */ 41 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE 42 43 #undef CONFIG_DM_MMC 44 #undef CONFIG_DM_PMIC 45 #undef CONFIG_DM_PMIC_PFUZE100 46 47 #define CONFIG_SYS_I2C 48 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 49 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 50 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 51 52 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 53 54 #define CONFIG_POWER 55 #define CONFIG_POWER_I2C 56 #define CONFIG_POWER_PFUZE100 57 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 58 #endif 59 60 #define CONFIG_REMAKE_ELF 61 62 /* ENET Config */ 63 /* ENET1 */ 64 #if defined(CONFIG_CMD_NET) 65 #define CONFIG_MII 66 #define CONFIG_ETHPRIME "FEC" 67 68 #define CONFIG_FEC_MXC 69 #define CONFIG_FEC_XCV_TYPE RGMII 70 #define CONFIG_FEC_MXC_PHYADDR 0 71 #define FEC_QUIRK_ENET_MAC 72 73 #define CONFIG_PHY_GIGE 74 #define IMX_FEC_BASE 0x30BE0000 75 #endif 76 77 #ifndef CONFIG_SPL_BUILD 78 #define BOOT_TARGET_DEVICES(func) \ 79 func(MMC, mmc, 0) \ 80 func(MMC, mmc, 1) \ 81 func(DHCP, dhcp, na) 82 83 #include <config_distro_bootcmd.h> 84 #endif 85 86 /* Initial environment variables */ 87 #define CONFIG_EXTRA_ENV_SETTINGS \ 88 BOOTENV \ 89 "scriptaddr=0x43500000\0" \ 90 "kernel_addr_r=0x40880000\0" \ 91 "image=Image\0" \ 92 "console=ttymxc0,115200\0" \ 93 "fdt_addr=0x43000000\0" \ 94 "boot_fdt=try\0" \ 95 "fdt_file=imx8mq-evk.dtb\0" \ 96 "initrd_addr=0x43800000\0" \ 97 "bootm_size=0x10000000\0" \ 98 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ 99 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ 100 101 /* Link Definitions */ 102 #define CONFIG_LOADADDR 0x40480000 103 104 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 105 106 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 107 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 108 #define CONFIG_SYS_INIT_SP_OFFSET \ 109 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 110 #define CONFIG_SYS_INIT_SP_ADDR \ 111 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 112 113 #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ 114 115 /* Size of malloc() pool */ 116 #define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024) 117 118 #define CONFIG_SYS_SDRAM_BASE 0x40000000 119 #define PHYS_SDRAM 0x40000000 120 #define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */ 121 122 #define CONFIG_MXC_UART_BASE UART1_BASE_ADDR 123 124 /* Monitor Command Prompt */ 125 #undef CONFIG_SYS_PROMPT 126 #define CONFIG_SYS_PROMPT "u-boot=> " 127 #define CONFIG_SYS_CBSIZE 1024 128 #define CONFIG_SYS_MAXARGS 64 129 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 130 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 131 sizeof(CONFIG_SYS_PROMPT) + 16) 132 133 #define CONFIG_IMX_BOOTAUX 134 135 #define CONFIG_SYS_FSL_USDHC_NUM 2 136 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 137 138 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 139 140 #define CONFIG_MXC_GPIO 141 142 /* I2C Configs */ 143 #define CONFIG_SYS_I2C_SPEED 100000 144 145 #define CONFIG_OF_SYSTEM_SETUP 146 147 #ifndef CONFIG_SPL_BUILD 148 #define CONFIG_DM_PMIC 149 #endif 150 151 #endif 152