1 /*
2  * High Level Configuration Options
3  */
4 #define CONFIG_KM8321	/* Keymile PBEC8321 board specific */
5 
6 /*
7  * System Clock Setup
8  */
9 #define CONFIG_83XX_CLKIN		66000000
10 #define CONFIG_SYS_CLK_FREQ		66000000
11 #define CONFIG_83XX_PCICLK		66000000
12 
13 /*
14  * System IO Config
15  */
16 #define CONFIG_SYS_SICRL	SICRL_IRQ_CKS
17 
18 #define CONFIG_SYS_DDRCDR (\
19 	DDRCDR_EN | \
20 	DDRCDR_PZ_MAXZ | \
21 	DDRCDR_NZ_MAXZ | \
22 	DDRCDR_M_ODR)
23 
24 #define CONFIG_SYS_DDR_CS0_BNDS		0x0000007f
25 #define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 | \
26 					 SDRAM_CFG_32_BE | \
27 					 SDRAM_CFG_SREN | \
28 					 SDRAM_CFG_HSE)
29 
30 #define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
31 #define CONFIG_SYS_DDR_CLK_CNTL		(DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
32 #define CONFIG_SYS_DDR_INTERVAL	((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
33 				 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
34 
35 #define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_AP | \
36 					 CSCONFIG_ODT_WR_CFG | \
37 					 CSCONFIG_ROW_BIT_13 | \
38 					 CSCONFIG_COL_BIT_10)
39 
40 #define CONFIG_SYS_DDR_MODE	0x47860242
41 #define CONFIG_SYS_DDR_MODE2	0x8080c000
42 
43 #define CONFIG_SYS_DDR_TIMING_0	((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
44 				 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
45 				 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
46 				 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
47 				 (0 << TIMING_CFG0_WWT_SHIFT) | \
48 				 (0 << TIMING_CFG0_RRT_SHIFT) | \
49 				 (0 << TIMING_CFG0_WRT_SHIFT) | \
50 				 (0 << TIMING_CFG0_RWT_SHIFT))
51 
52 #define CONFIG_SYS_DDR_TIMING_1	((TIMING_CFG1_CASLAT_40) | \
53 				 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
54 				 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
55 				 (3 << TIMING_CFG1_WRREC_SHIFT) | \
56 				 (7 << TIMING_CFG1_REFREC_SHIFT) | \
57 				 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
58 				 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
59 				 (3 << TIMING_CFG1_PRETOACT_SHIFT))
60 
61 #define CONFIG_SYS_DDR_TIMING_2	((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
62 				 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
63 				 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
64 				 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
65 				 (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
66 				 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
67 				 (5 << TIMING_CFG2_CPO_SHIFT))
68 
69 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
70 
71 #define CONFIG_SYS_KMBEC_FPGA_BASE	0xE8000000
72 #define CONFIG_SYS_KMBEC_FPGA_SIZE	128
73 
74 /* EEprom support */
75 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
76 
77