1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2016 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __LS1012AQDS_H__ 7 #define __LS1012AQDS_H__ 8 9 #include "ls1012a_common.h" 10 11 /* DDR */ 12 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 13 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 14 #define CONFIG_SYS_SDRAM_SIZE 0x40000000 15 16 /* 17 * QIXIS Definitions 18 */ 19 #define CONFIG_FSL_QIXIS 20 21 #ifdef CONFIG_FSL_QIXIS 22 #define CONFIG_QIXIS_I2C_ACCESS 23 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 24 #define QIXIS_LBMAP_BRDCFG_REG 0x04 25 #define QIXIS_LBMAP_SWITCH 6 26 #define QIXIS_LBMAP_MASK 0x08 27 #define QIXIS_LBMAP_SHIFT 0 28 #define QIXIS_LBMAP_DFLTBANK 0x00 29 #define QIXIS_LBMAP_ALTBANK 0x08 30 #define QIXIS_RST_CTL_RESET 0x31 31 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 32 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 33 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 34 #endif 35 36 /* 37 * I2C bus multiplexer 38 */ 39 #define I2C_MUX_PCA_ADDR_PRI 0x77 40 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 41 #define I2C_RETIMER_ADDR 0x18 42 #define I2C_MUX_CH_DEFAULT 0x8 43 #define I2C_MUX_CH_CH7301 0xC 44 #define I2C_MUX_CH5 0xD 45 #define I2C_MUX_CH7 0xF 46 47 #define I2C_MUX_CH_VOL_MONITOR 0xa 48 49 /* 50 * RTC configuration 51 */ 52 #define RTC 53 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ 54 55 /* EEPROM */ 56 #define CONFIG_ID_EEPROM 57 #define CONFIG_SYS_I2C_EEPROM_NXID 58 #define CONFIG_SYS_EEPROM_BUS_NUM 0 59 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 60 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 61 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 62 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 63 64 65 /* Voltage monitor on channel 2*/ 66 #define I2C_VOL_MONITOR_ADDR 0x40 67 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 68 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 69 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 70 71 /* DSPI */ 72 #define CONFIG_FSL_DSPI1 73 74 #define MMAP_DSPI DSPI1_BASE_ADDR 75 76 #define CONFIG_SYS_DSPI_CTAR0 1 77 78 #define CONFIG_SYS_DSPI_CTAR1 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\ 79 DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \ 80 DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \ 81 DSPI_CTAR_DT(0)) 82 #define CONFIG_SPI_FLASH_SST /* cs1 */ 83 84 #define CONFIG_SYS_DSPI_CTAR2 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\ 85 DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \ 86 DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \ 87 DSPI_CTAR_DT(0)) 88 #define CONFIG_SPI_FLASH_STMICRO /* cs2 */ 89 90 #define CONFIG_SYS_DSPI_CTAR3 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\ 91 DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \ 92 DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \ 93 DSPI_CTAR_DT(0)) 94 #define CONFIG_SPI_FLASH_EON /* cs3 */ 95 96 /* MMC */ 97 #ifdef CONFIG_MMC 98 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 99 #endif 100 101 #define CONFIG_PCIE1 /* PCIE controller 1 */ 102 103 #define CONFIG_PCI_SCAN_SHOW 104 105 #undef CONFIG_EXTRA_ENV_SETTINGS 106 #define CONFIG_EXTRA_ENV_SETTINGS \ 107 "verify=no\0" \ 108 "fdt_addr=0x00f00000\0" \ 109 "kernel_addr=0x01000000\0" \ 110 "kernelheader_addr=0x600000\0" \ 111 "scriptaddr=0x80000000\0" \ 112 "scripthdraddr=0x80080000\0" \ 113 "fdtheader_addr_r=0x80100000\0" \ 114 "kernelheader_addr_r=0x80200000\0" \ 115 "kernel_addr_r=0x96000000\0" \ 116 "fdt_addr_r=0x90000000\0" \ 117 "load_addr=0xa0000000\0" \ 118 "kernel_size=0x2800000\0" \ 119 "kernelheader_size=0x40000\0" \ 120 "console=ttyS0,115200\0" \ 121 BOOTENV \ 122 "boot_scripts=ls1012aqds_boot.scr\0" \ 123 "boot_script_hdr=hdr_ls1012aqds_bs.out\0" \ 124 "scan_dev_for_boot_part=" \ 125 "part list ${devtype} ${devnum} devplist; " \ 126 "env exists devplist || setenv devplist 1; " \ 127 "for distro_bootpart in ${devplist}; do " \ 128 "if fstype ${devtype} " \ 129 "${devnum}:${distro_bootpart} " \ 130 "bootfstype; then " \ 131 "run scan_dev_for_boot; " \ 132 "fi; " \ 133 "done\0" \ 134 "scan_dev_for_boot=" \ 135 "echo Scanning ${devtype} " \ 136 "${devnum}:${distro_bootpart}...; " \ 137 "for prefix in ${boot_prefixes}; do " \ 138 "run scan_dev_for_scripts; " \ 139 "done;" \ 140 "\0" \ 141 "boot_a_script=" \ 142 "load ${devtype} ${devnum}:${distro_bootpart} " \ 143 "${scriptaddr} ${prefix}${script}; " \ 144 "env exists secureboot && load ${devtype} " \ 145 "${devnum}:${distro_bootpart} " \ 146 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \ 147 "env exists secureboot " \ 148 "&& esbc_validate ${scripthdraddr};" \ 149 "source ${scriptaddr}\0" \ 150 "qspi_bootcmd=pfe stop; echo Trying load from qspi..;" \ 151 "sf probe 0:0 && sf read $load_addr " \ 152 "$kernel_addr $kernel_size; env exists secureboot " \ 153 "&& sf read $kernelheader_addr_r $kernelheader_addr " \ 154 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ 155 "bootm $load_addr#$board\0" 156 157 #undef CONFIG_BOOTCOMMAND 158 #ifdef CONFIG_TFABOOT 159 #undef QSPI_NOR_BOOTCOMMAND 160 #define QSPI_NOR_BOOTCOMMAND "pfe stop; run distro_bootcmd; run qspi_bootcmd; "\ 161 "env exists secureboot && esbc_halt;" 162 #else 163 #define CONFIG_BOOTCOMMAND "pfe stop; run distro_bootcmd; run qspi_bootcmd; "\ 164 "env exists secureboot && esbc_halt;" 165 #endif 166 167 #include <asm/fsl_secure_boot.h> 168 #endif /* __LS1012AQDS_H__ */ 169