1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2016 Freescale Semiconductor 4 * Copyright 2019-2020 NXP 5 */ 6 7 #ifndef __LS1046A_COMMON_H 8 #define __LS1046A_COMMON_H 9 10 /* SPL build */ 11 #ifdef CONFIG_SPL_BUILD 12 #define SPL_NO_QBMAN 13 #define SPL_NO_FMAN 14 #define SPL_NO_ENV 15 #define SPL_NO_MISC 16 #define SPL_NO_QSPI 17 #define SPL_NO_USB 18 #define SPL_NO_SATA 19 #endif 20 #if defined(CONFIG_SPL_BUILD) && \ 21 (defined(CONFIG_NAND_BOOT) || defined(CONFIG_QSPI_BOOT)) 22 #define SPL_NO_MMC 23 #endif 24 #if defined(CONFIG_SPL_BUILD) && \ 25 !defined(CONFIG_SPL_FSL_LS_PPA) 26 #define SPL_NO_IFC 27 #endif 28 29 #define CONFIG_REMAKE_ELF 30 #define CONFIG_GICV2 31 32 #include <asm/arch/config.h> 33 #include <asm/arch/stream_id_lsch2.h> 34 35 /* Link Definitions */ 36 #ifdef CONFIG_TFABOOT 37 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE 38 #else 39 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 40 #endif 41 42 #define CONFIG_SKIP_LOWLEVEL_INIT 43 44 #define CONFIG_VERY_BIG_RAM 45 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 46 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 47 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 48 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL 49 50 #define CPU_RELEASE_ADDR secondary_boot_addr 51 52 /* Generic Timer Definitions */ 53 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 54 55 /* Size of malloc() pool */ 56 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) 57 58 /* Serial Port */ 59 #define CONFIG_SYS_NS16550_SERIAL 60 #define CONFIG_SYS_NS16550_REG_SIZE 1 61 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) 62 63 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 64 65 /* SD boot SPL */ 66 #ifdef CONFIG_SD_BOOT 67 #define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */ 68 #define CONFIG_SPL_STACK 0x10020000 69 #define CONFIG_SPL_PAD_TO 0x21000 /* 132 KiB */ 70 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000 71 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 72 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 73 CONFIG_SPL_BSS_MAX_SIZE) 74 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 75 76 #ifdef CONFIG_NXP_ESBC 77 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 78 /* 79 * HDR would be appended at end of image and copied to DDR along 80 * with U-Boot image. Here u-boot max. size is 512K. So if binary 81 * size increases then increase this size in case of secure boot as 82 * it uses raw u-boot image instead of fit image. 83 */ 84 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) 85 #else 86 #define CONFIG_SYS_MONITOR_LEN 0x100000 87 #endif /* ifdef CONFIG_NXP_ESBC */ 88 #endif 89 90 #if defined(CONFIG_QSPI_BOOT) && defined(CONFIG_SPL) 91 #define CONFIG_SPL_TARGET "spl/u-boot-spl.pbl" 92 #define CONFIG_SPL_MAX_SIZE 0x1f000 93 #define CONFIG_SPL_STACK 0x10020000 94 #define CONFIG_SPL_PAD_TO 0x20000 95 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000 96 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 97 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 98 CONFIG_SPL_BSS_MAX_SIZE) 99 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 100 #define CONFIG_SYS_MONITOR_LEN 0x100000 101 #endif 102 103 /* NAND SPL */ 104 #ifdef CONFIG_NAND_BOOT 105 #define CONFIG_SPL_PBL_PAD 106 #define CONFIG_SPL_LIBCOMMON_SUPPORT 107 #define CONFIG_SPL_LIBGENERIC_SUPPORT 108 #define CONFIG_SPL_ENV_SUPPORT 109 #define CONFIG_SPL_WATCHDOG_SUPPORT 110 #define CONFIG_SPL_I2C_SUPPORT 111 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 112 113 #define CONFIG_SPL_NAND_SUPPORT 114 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 115 #define CONFIG_SPL_MAX_SIZE 0x17000 /* 90 KiB */ 116 #define CONFIG_SPL_STACK 0x1001f000 117 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 118 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 119 120 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000 121 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 122 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 123 CONFIG_SPL_BSS_MAX_SIZE) 124 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 125 #define CONFIG_SYS_MONITOR_LEN 0xa0000 126 #endif 127 128 /* GPIO */ 129 #ifdef CONFIG_DM_GPIO 130 #ifndef CONFIG_MPC8XXX_GPIO 131 #define CONFIG_MPC8XXX_GPIO 132 #endif 133 #endif 134 135 /* I2C */ 136 #if !CONFIG_IS_ENABLED(DM_I2C) 137 #define CONFIG_SYS_I2C 138 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 139 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 140 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 141 #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ 142 #else 143 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM 144 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 145 #endif 146 147 /* PCIe */ 148 #define CONFIG_PCIE1 /* PCIE controller 1 */ 149 #define CONFIG_PCIE2 /* PCIE controller 2 */ 150 #define CONFIG_PCIE3 /* PCIE controller 3 */ 151 152 #ifdef CONFIG_PCI 153 #define CONFIG_PCI_SCAN_SHOW 154 #endif 155 156 /* SATA */ 157 #ifndef SPL_NO_SATA 158 #define CONFIG_SCSI_AHCI_PLAT 159 160 #define CONFIG_SYS_SATA AHCI_BASE_ADDR 161 162 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 163 #define CONFIG_SYS_SCSI_MAX_LUN 1 164 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 165 CONFIG_SYS_SCSI_MAX_LUN) 166 #endif 167 168 /* MMC */ 169 #ifndef SPL_NO_MMC 170 #ifdef CONFIG_MMC 171 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 172 #endif 173 #endif 174 175 /* FMan ucode */ 176 #ifndef SPL_NO_FMAN 177 #define CONFIG_SYS_DPAA_FMAN 178 #ifdef CONFIG_SYS_DPAA_FMAN 179 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 180 #endif 181 182 #ifdef CONFIG_TFABOOT 183 #define CONFIG_SYS_FMAN_FW_ADDR 0x900000 184 #else 185 #ifdef CONFIG_SD_BOOT 186 /* 187 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 188 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 189 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 18432(0x4800). 190 */ 191 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800) 192 #elif defined(CONFIG_QSPI_BOOT) 193 #define CONFIG_SYS_FMAN_FW_ADDR 0x40900000 194 #elif defined(CONFIG_NAND_BOOT) 195 #define CONFIG_SYS_FMAN_FW_ADDR (36 * CONFIG_SYS_NAND_BLOCK_SIZE) 196 #else 197 #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000 198 #endif 199 #endif 200 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 201 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 202 #endif 203 204 /* Miscellaneous configurable options */ 205 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 206 207 #define CONFIG_HWCONFIG 208 #define HWCONFIG_BUFFER_SIZE 128 209 210 #ifndef CONFIG_SPL_BUILD 211 #define BOOT_TARGET_DEVICES(func) \ 212 func(SCSI, scsi, 0) \ 213 func(MMC, mmc, 0) \ 214 func(USB, usb, 0) \ 215 func(DHCP, dhcp, na) 216 #include <config_distro_bootcmd.h> 217 #endif 218 219 #if defined(CONFIG_TARGET_LS1046AFRWY) 220 #define LS1046A_BOOT_SRC_AND_HDR\ 221 "boot_scripts=ls1046afrwy_boot.scr\0" \ 222 "boot_script_hdr=hdr_ls1046afrwy_bs.out\0" 223 #elif defined(CONFIG_TARGET_LS1046AQDS) 224 #define LS1046A_BOOT_SRC_AND_HDR\ 225 "boot_scripts=ls1046aqds_boot.scr\0" \ 226 "boot_script_hdr=hdr_ls1046aqds_bs.out\0" 227 #else 228 #define LS1046A_BOOT_SRC_AND_HDR\ 229 "boot_scripts=ls1046ardb_boot.scr\0" \ 230 "boot_script_hdr=hdr_ls1046ardb_bs.out\0" 231 #endif 232 #ifndef SPL_NO_MISC 233 /* Initial environment variables */ 234 #define CONFIG_EXTRA_ENV_SETTINGS \ 235 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 236 "ramdisk_addr=0x800000\0" \ 237 "ramdisk_size=0x2000000\0" \ 238 "bootm_size=0x10000000\0" \ 239 "fdt_addr=0x64f00000\0" \ 240 "kernel_addr=0x61000000\0" \ 241 "scriptaddr=0x80000000\0" \ 242 "scripthdraddr=0x80080000\0" \ 243 "fdtheader_addr_r=0x80100000\0" \ 244 "kernelheader_addr_r=0x80200000\0" \ 245 "load_addr=0xa0000000\0" \ 246 "kernel_addr_r=0x81000000\0" \ 247 "fdt_addr_r=0x90000000\0" \ 248 "ramdisk_addr_r=0xa0000000\0" \ 249 "kernel_start=0x1000000\0" \ 250 "kernelheader_start=0x600000\0" \ 251 "kernel_load=0xa0000000\0" \ 252 "kernel_size=0x2800000\0" \ 253 "kernelheader_size=0x40000\0" \ 254 "kernel_addr_sd=0x8000\0" \ 255 "kernel_size_sd=0x14000\0" \ 256 "kernelhdr_addr_sd=0x3000\0" \ 257 "kernelhdr_size_sd=0x10\0" \ 258 "console=ttyS0,115200\0" \ 259 CONFIG_MTDPARTS_DEFAULT "\0" \ 260 BOOTENV \ 261 LS1046A_BOOT_SRC_AND_HDR \ 262 "scan_dev_for_boot_part=" \ 263 "part list ${devtype} ${devnum} devplist; " \ 264 "env exists devplist || setenv devplist 1; " \ 265 "for distro_bootpart in ${devplist}; do " \ 266 "if fstype ${devtype} " \ 267 "${devnum}:${distro_bootpart} " \ 268 "bootfstype; then " \ 269 "run scan_dev_for_boot; " \ 270 "fi; " \ 271 "done\0" \ 272 "boot_a_script=" \ 273 "load ${devtype} ${devnum}:${distro_bootpart} " \ 274 "${scriptaddr} ${prefix}${script}; " \ 275 "env exists secureboot && load ${devtype} " \ 276 "${devnum}:${distro_bootpart} " \ 277 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \ 278 "env exists secureboot " \ 279 "&& esbc_validate ${scripthdraddr};" \ 280 "source ${scriptaddr}\0" \ 281 "qspi_bootcmd=echo Trying load from qspi..;" \ 282 "sf probe && sf read $load_addr " \ 283 "$kernel_start $kernel_size; env exists secureboot " \ 284 "&& sf read $kernelheader_addr_r $kernelheader_start " \ 285 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ 286 "bootm $load_addr#$board\0" \ 287 "nand_bootcmd=echo Trying load from nand..;" \ 288 "nand info; nand read $load_addr " \ 289 "$kernel_start $kernel_size; env exists secureboot " \ 290 "&& nand read $kernelheader_addr_r $kernelheader_start " \ 291 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ 292 "bootm $load_addr#$board\0" \ 293 "nor_bootcmd=echo Trying load from nor..;" \ 294 "cp.b $kernel_addr $load_addr " \ 295 "$kernel_size; env exists secureboot " \ 296 "&& cp.b $kernelheader_addr $kernelheader_addr_r " \ 297 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ 298 "bootm $load_addr#$board\0" \ 299 "sd_bootcmd=echo Trying load from SD ..;" \ 300 "mmcinfo; mmc read $load_addr " \ 301 "$kernel_addr_sd $kernel_size_sd && " \ 302 "env exists secureboot && mmc read $kernelheader_addr_r " \ 303 "$kernelhdr_addr_sd $kernelhdr_size_sd " \ 304 " && esbc_validate ${kernelheader_addr_r};" \ 305 "bootm $load_addr#$board\0" 306 307 #endif 308 309 /* Monitor Command Prompt */ 310 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 311 312 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 313 314 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 315 316 #include <asm/arch/soc.h> 317 318 #endif /* __LS1046A_COMMON_H */ 319