1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2016 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __LS1046AQDS_H__ 7 #define __LS1046AQDS_H__ 8 9 #include "ls1046a_common.h" 10 11 #ifndef __ASSEMBLY__ 12 unsigned long get_board_sys_clk(void); 13 unsigned long get_board_ddr_clk(void); 14 #endif 15 16 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 17 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 18 19 #define CONFIG_SKIP_LOWLEVEL_INIT 20 21 #define CONFIG_LAYERSCAPE_NS_ACCESS 22 23 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 24 /* Physical Memory Map */ 25 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 26 27 #define CONFIG_DDR_SPD 28 #define SPD_EEPROM_ADDRESS 0x51 29 #define CONFIG_SYS_SPD_BUS_NUM 0 30 31 #define CONFIG_DDR_ECC 32 #ifdef CONFIG_DDR_ECC 33 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 34 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 35 #endif 36 37 /* DSPI */ 38 #ifdef CONFIG_FSL_DSPI 39 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */ 40 #define CONFIG_SPI_FLASH_SST /* cs1 */ 41 #define CONFIG_SPI_FLASH_EON /* cs2 */ 42 #endif 43 44 #ifdef CONFIG_SYS_DPAA_FMAN 45 #define RGMII_PHY1_ADDR 0x1 46 #define RGMII_PHY2_ADDR 0x2 47 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 48 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 49 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 50 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 51 /* PHY address on QSGMII riser card on slot 2 */ 52 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8 53 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9 54 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA 55 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB 56 #endif 57 58 #ifdef CONFIG_RAMBOOT_PBL 59 #define CONFIG_SYS_FSL_PBL_PBI \ 60 board/freescale/ls1046aqds/ls1046aqds_pbi.cfg 61 #endif 62 63 #ifdef CONFIG_NAND_BOOT 64 #define CONFIG_SYS_FSL_PBL_RCW \ 65 board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg 66 #endif 67 68 #ifdef CONFIG_SD_BOOT 69 #ifdef CONFIG_SD_BOOT_QSPI 70 #define CONFIG_SYS_FSL_PBL_RCW \ 71 board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg 72 #else 73 #define CONFIG_SYS_FSL_PBL_RCW \ 74 board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg 75 #endif 76 #endif 77 78 /* IFC */ 79 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 80 #define CONFIG_FSL_IFC 81 /* 82 * CONFIG_SYS_FLASH_BASE has the final address (core view) 83 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 84 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 85 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting 86 */ 87 #define CONFIG_SYS_FLASH_BASE 0x60000000 88 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 89 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 90 91 #ifdef CONFIG_MTD_NOR_FLASH 92 #define CONFIG_SYS_FLASH_QUIET_TEST 93 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 94 #endif 95 #endif 96 97 /* LPUART */ 98 #ifdef CONFIG_LPUART 99 #define CONFIG_LPUART_32B_REG 100 #define CFG_UART_MUX_MASK 0x6 101 #define CFG_UART_MUX_SHIFT 1 102 #define CFG_LPUART_EN 0x2 103 #endif 104 105 /* EEPROM */ 106 #define CONFIG_ID_EEPROM 107 #define CONFIG_SYS_I2C_EEPROM_NXID 108 #define CONFIG_SYS_EEPROM_BUS_NUM 0 109 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 110 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 111 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 112 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 113 114 /* 115 * IFC Definitions 116 */ 117 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 118 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 119 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 120 CSPR_PORT_SIZE_16 | \ 121 CSPR_MSEL_NOR | \ 122 CSPR_V) 123 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 124 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 125 + 0x8000000) | \ 126 CSPR_PORT_SIZE_16 | \ 127 CSPR_MSEL_NOR | \ 128 CSPR_V) 129 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 130 131 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 132 CSOR_NOR_TRHZ_80) 133 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 134 FTIM0_NOR_TEADC(0x5) | \ 135 FTIM0_NOR_TAVDS(0x6) | \ 136 FTIM0_NOR_TEAHC(0x5)) 137 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 138 FTIM1_NOR_TRAD_NOR(0x1a) | \ 139 FTIM1_NOR_TSEQRAD_NOR(0x13)) 140 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \ 141 FTIM2_NOR_TCH(0x8) | \ 142 FTIM2_NOR_TWPH(0xe) | \ 143 FTIM2_NOR_TWP(0x1c)) 144 #define CONFIG_SYS_NOR_FTIM3 0 145 146 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 147 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 148 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 149 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 150 151 #define CONFIG_SYS_FLASH_EMPTY_INFO 152 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 153 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 154 155 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 156 #define CONFIG_SYS_WRITE_SWAPPED_DATA 157 158 /* 159 * NAND Flash Definitions 160 */ 161 #define CONFIG_NAND_FSL_IFC 162 163 #define CONFIG_SYS_NAND_BASE 0x7e800000 164 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 165 166 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 167 168 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 169 | CSPR_PORT_SIZE_8 \ 170 | CSPR_MSEL_NAND \ 171 | CSPR_V) 172 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 173 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 174 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 175 | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \ 176 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 177 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 178 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 179 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 180 181 #define CONFIG_SYS_NAND_ONFI_DETECTION 182 183 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 184 FTIM0_NAND_TWP(0x18) | \ 185 FTIM0_NAND_TWCHT(0x7) | \ 186 FTIM0_NAND_TWH(0xa)) 187 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 188 FTIM1_NAND_TWBE(0x39) | \ 189 FTIM1_NAND_TRR(0xe) | \ 190 FTIM1_NAND_TRP(0x18)) 191 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 192 FTIM2_NAND_TREH(0xa) | \ 193 FTIM2_NAND_TWHRE(0x1e)) 194 #define CONFIG_SYS_NAND_FTIM3 0x0 195 196 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 197 #define CONFIG_SYS_MAX_NAND_DEVICE 1 198 #define CONFIG_MTD_NAND_VERIFY_WRITE 199 200 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) 201 #endif 202 203 #ifdef CONFIG_NAND_BOOT 204 #define CONFIG_SPL_PAD_TO 0x40000 /* block aligned */ 205 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 206 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 207 #endif 208 209 #if defined(CONFIG_TFABOOT) || \ 210 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 211 #define CONFIG_QIXIS_I2C_ACCESS 212 #define CONFIG_SYS_I2C_EARLY_INIT 213 #endif 214 215 /* 216 * QIXIS Definitions 217 */ 218 #define CONFIG_FSL_QIXIS 219 220 #ifdef CONFIG_FSL_QIXIS 221 #define QIXIS_BASE 0x7fb00000 222 #define QIXIS_BASE_PHYS QIXIS_BASE 223 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 224 #define QIXIS_LBMAP_SWITCH 6 225 #define QIXIS_LBMAP_MASK 0x0f 226 #define QIXIS_LBMAP_SHIFT 0 227 #define QIXIS_LBMAP_DFLTBANK 0x00 228 #define QIXIS_LBMAP_ALTBANK 0x04 229 #define QIXIS_LBMAP_NAND 0x09 230 #define QIXIS_LBMAP_SD 0x00 231 #define QIXIS_LBMAP_SD_QSPI 0xff 232 #define QIXIS_LBMAP_QSPI 0xff 233 #define QIXIS_RCW_SRC_NAND 0x110 234 #define QIXIS_RCW_SRC_SD 0x040 235 #define QIXIS_RCW_SRC_QSPI 0x045 236 #define QIXIS_RST_CTL_RESET 0x41 237 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 238 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 239 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 240 241 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 242 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 243 CSPR_PORT_SIZE_8 | \ 244 CSPR_MSEL_GPCM | \ 245 CSPR_V) 246 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 247 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 248 CSOR_NOR_NOR_MODE_AVD_NOR | \ 249 CSOR_NOR_TRHZ_80) 250 251 /* 252 * QIXIS Timing parameters for IFC GPCM 253 */ 254 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ 255 FTIM0_GPCM_TEADC(0x20) | \ 256 FTIM0_GPCM_TEAHC(0x10)) 257 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ 258 FTIM1_GPCM_TRAD(0x1f)) 259 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ 260 FTIM2_GPCM_TCH(0x8) | \ 261 FTIM2_GPCM_TWP(0xf0)) 262 #define CONFIG_SYS_FPGA_FTIM3 0x0 263 #endif 264 265 #ifdef CONFIG_TFABOOT 266 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 267 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 268 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 269 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 270 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 271 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 272 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 273 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 274 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 275 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 276 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 277 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 278 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 279 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 280 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 281 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 282 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 283 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 284 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 285 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 286 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 287 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 288 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 289 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 290 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 291 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 292 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 293 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 294 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 295 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 296 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 297 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 298 #else 299 #ifdef CONFIG_NAND_BOOT 300 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 301 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 302 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 303 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 304 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 305 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 306 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 307 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 308 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 309 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 310 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 311 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 312 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 313 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 314 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 315 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 316 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 317 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 318 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 319 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 320 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 321 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 322 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 323 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 324 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 325 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 326 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 327 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 328 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 329 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 330 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 331 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 332 #else 333 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 334 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 335 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 336 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 337 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 338 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 339 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 340 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 341 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 342 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 343 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 344 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 345 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 346 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 347 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 348 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 349 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 350 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 351 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 352 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 353 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 354 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 355 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 356 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 357 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 358 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 359 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 360 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 361 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 362 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 363 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 364 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 365 #endif 366 #endif 367 368 /* 369 * I2C bus multiplexer 370 */ 371 #define I2C_MUX_PCA_ADDR_PRI 0x77 372 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 373 #define I2C_RETIMER_ADDR 0x18 374 #define I2C_MUX_CH_DEFAULT 0x8 375 #define I2C_MUX_CH_CH7301 0xC 376 #define I2C_MUX_CH5 0xD 377 #define I2C_MUX_CH6 0xE 378 #define I2C_MUX_CH7 0xF 379 380 #define I2C_MUX_CH_VOL_MONITOR 0xa 381 382 /* Voltage monitor on channel 2*/ 383 #define I2C_VOL_MONITOR_ADDR 0x40 384 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 385 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 386 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 387 388 #define CONFIG_VID_FLS_ENV "ls1046aqds_vdd_mv" 389 #ifndef CONFIG_SPL_BUILD 390 #define CONFIG_VID 391 #endif 392 #define CONFIG_VOL_MONITOR_IR36021_SET 393 #define CONFIG_VOL_MONITOR_INA220 394 /* The lowest and highest voltage allowed for LS1046AQDS */ 395 #define VDD_MV_MIN 819 396 #define VDD_MV_MAX 1212 397 398 /* 399 * Miscellaneous configurable options 400 */ 401 402 #define CONFIG_SYS_HZ 1000 403 404 #define CONFIG_SYS_INIT_SP_OFFSET \ 405 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 406 407 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 408 409 /* 410 * Environment 411 */ 412 413 #define CONFIG_CMDLINE_TAG 414 415 #undef CONFIG_BOOTCOMMAND 416 #ifdef CONFIG_TFABOOT 417 #define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \ 418 "env exists secureboot && esbc_halt;;" 419 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd" \ 420 "env exists secureboot && esbc_halt;;" 421 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \ 422 "env exists secureboot && esbc_halt;;" 423 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ 424 "env exists secureboot && esbc_halt;;" 425 #else 426 #if defined(CONFIG_QSPI_BOOT) 427 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \ 428 "env exists secureboot && esbc_halt;;" 429 #elif defined(CONFIG_NAND_BOOT) 430 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \ 431 "env exists secureboot && esbc_halt;;" 432 #elif defined(CONFIG_SD_BOOT) 433 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ 434 "env exists secureboot && esbc_halt;;" 435 #else 436 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \ 437 "env exists secureboot && esbc_halt;;" 438 #endif 439 #endif 440 441 #include <asm/fsl_secure_boot.h> 442 443 #endif /* __LS1046AQDS_H__ */ 444