1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2017, 2019-2020 NXP 4 * Copyright 2015 Freescale Semiconductor 5 */ 6 7 #ifndef __LS2_QDS_H 8 #define __LS2_QDS_H 9 10 #include "ls2080a_common.h" 11 12 #ifndef __ASSEMBLY__ 13 unsigned long get_board_sys_clk(void); 14 unsigned long get_board_ddr_clk(void); 15 #endif 16 17 #ifdef CONFIG_FSL_QSPI 18 #define CONFIG_QIXIS_I2C_ACCESS 19 #if !CONFIG_IS_ENABLED(DM_I2C) 20 #define CONFIG_SYS_I2C_EARLY_INIT 21 #endif 22 #define CONFIG_SYS_I2C_IFDR_DIV 0x7e 23 #endif 24 25 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 26 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 27 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 28 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) 29 30 #define CONFIG_DDR_SPD 31 #define CONFIG_DDR_ECC 32 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 33 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 34 #define SPD_EEPROM_ADDRESS1 0x51 35 #define SPD_EEPROM_ADDRESS2 0x52 36 #define SPD_EEPROM_ADDRESS3 0x53 37 #define SPD_EEPROM_ADDRESS4 0x54 38 #define SPD_EEPROM_ADDRESS5 0x55 39 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ 40 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 41 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ 42 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 43 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 44 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 45 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 46 #endif 47 48 /* SATA */ 49 #define CONFIG_SCSI_AHCI_PLAT 50 51 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 52 #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 53 54 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 55 #define CONFIG_SYS_SCSI_MAX_LUN 1 56 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 57 CONFIG_SYS_SCSI_MAX_LUN) 58 59 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 60 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 61 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) 62 63 #define CONFIG_SYS_NOR0_CSPR \ 64 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 65 CSPR_PORT_SIZE_16 | \ 66 CSPR_MSEL_NOR | \ 67 CSPR_V) 68 #define CONFIG_SYS_NOR0_CSPR_EARLY \ 69 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 70 CSPR_PORT_SIZE_16 | \ 71 CSPR_MSEL_NOR | \ 72 CSPR_V) 73 #define CONFIG_SYS_NOR1_CSPR \ 74 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ 75 CSPR_PORT_SIZE_16 | \ 76 CSPR_MSEL_NOR | \ 77 CSPR_V) 78 #define CONFIG_SYS_NOR1_CSPR_EARLY \ 79 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ 80 CSPR_PORT_SIZE_16 | \ 81 CSPR_MSEL_NOR | \ 82 CSPR_V) 83 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) 84 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 85 FTIM0_NOR_TEADC(0x5) | \ 86 FTIM0_NOR_TEAHC(0x5)) 87 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 88 FTIM1_NOR_TRAD_NOR(0x1a) |\ 89 FTIM1_NOR_TSEQRAD_NOR(0x13)) 90 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 91 FTIM2_NOR_TCH(0x4) | \ 92 FTIM2_NOR_TWPH(0x0E) | \ 93 FTIM2_NOR_TWP(0x1c)) 94 #define CONFIG_SYS_NOR_FTIM3 0x04000000 95 #define CONFIG_SYS_IFC_CCR 0x01000000 96 97 #ifdef CONFIG_MTD_NOR_FLASH 98 #define CONFIG_SYS_FLASH_QUIET_TEST 99 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 100 101 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 102 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 103 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 104 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 105 106 #define CONFIG_SYS_FLASH_EMPTY_INFO 107 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ 108 CONFIG_SYS_FLASH_BASE + 0x40000000} 109 #endif 110 111 #define CONFIG_NAND_FSL_IFC 112 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 113 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 114 115 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 116 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 117 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 118 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 119 | CSPR_V) 120 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 121 122 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 123 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 124 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 125 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 126 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 127 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 128 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 129 130 #define CONFIG_SYS_NAND_ONFI_DETECTION 131 132 /* ONFI NAND Flash mode0 Timing Params */ 133 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 134 FTIM0_NAND_TWP(0x18) | \ 135 FTIM0_NAND_TWCHT(0x07) | \ 136 FTIM0_NAND_TWH(0x0a)) 137 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 138 FTIM1_NAND_TWBE(0x39) | \ 139 FTIM1_NAND_TRR(0x0e) | \ 140 FTIM1_NAND_TRP(0x18)) 141 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 142 FTIM2_NAND_TREH(0x0a) | \ 143 FTIM2_NAND_TWHRE(0x1e)) 144 #define CONFIG_SYS_NAND_FTIM3 0x0 145 146 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 147 #define CONFIG_SYS_MAX_NAND_DEVICE 1 148 #define CONFIG_MTD_NAND_VERIFY_WRITE 149 150 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 151 152 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 153 #define QIXIS_LBMAP_SWITCH 0x06 154 #define QIXIS_LBMAP_MASK 0x0f 155 #define QIXIS_LBMAP_SHIFT 0 156 #define QIXIS_LBMAP_DFLTBANK 0x00 157 #define QIXIS_LBMAP_ALTBANK 0x04 158 #define QIXIS_LBMAP_NAND 0x09 159 #define QIXIS_LBMAP_SD 0x00 160 #define QIXIS_LBMAP_QSPI 0x0f 161 #define QIXIS_RST_CTL_RESET 0x31 162 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 163 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 164 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 165 #define QIXIS_RCW_SRC_NAND 0x107 166 #define QIXIS_RCW_SRC_SD 0x40 167 #define QIXIS_RCW_SRC_QSPI 0x62 168 #define QIXIS_RST_FORCE_MEM 0x01 169 170 #define CONFIG_SYS_CSPR3_EXT (0x0) 171 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 172 | CSPR_PORT_SIZE_8 \ 173 | CSPR_MSEL_GPCM \ 174 | CSPR_V) 175 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 176 | CSPR_PORT_SIZE_8 \ 177 | CSPR_MSEL_GPCM \ 178 | CSPR_V) 179 180 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 181 #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) 182 /* QIXIS Timing parameters for IFC CS3 */ 183 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 184 FTIM0_GPCM_TEADC(0x0e) | \ 185 FTIM0_GPCM_TEAHC(0x0e)) 186 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 187 FTIM1_GPCM_TRAD(0x3f)) 188 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 189 FTIM2_GPCM_TCH(0xf) | \ 190 FTIM2_GPCM_TWP(0x3E)) 191 #define CONFIG_SYS_CS3_FTIM3 0x0 192 193 #if defined(CONFIG_SPL) 194 #if defined(CONFIG_NAND_BOOT) 195 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 196 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY 197 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR 198 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 199 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 200 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 201 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 202 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 203 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 204 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 205 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY 206 #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR 207 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY 208 #define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK 209 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 210 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 211 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 212 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 213 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 214 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 215 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 216 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 217 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 218 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 219 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 220 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 221 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 222 223 #define CONFIG_SPL_PAD_TO 0x20000 224 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024) 225 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024) 226 #endif 227 #else 228 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 229 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 230 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 231 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 232 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 233 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 234 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 235 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 236 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 237 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 238 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY 239 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR 240 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY 241 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK 242 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 243 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 244 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 245 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 246 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 247 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 248 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 249 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 250 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 251 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 252 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 253 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 254 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 255 #endif 256 257 /* Debug Server firmware */ 258 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR 259 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL 260 261 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 262 263 /* 264 * I2C 265 */ 266 #define I2C_MUX_PCA_ADDR 0x77 267 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 268 269 /* I2C bus multiplexer */ 270 #define I2C_MUX_CH_DEFAULT 0x8 271 272 /* SPI */ 273 #ifdef CONFIG_FSL_DSPI 274 #define CONFIG_SPI_FLASH_STMICRO 275 #define CONFIG_SPI_FLASH_SST 276 #define CONFIG_SPI_FLASH_EON 277 #endif 278 279 #ifdef CONFIG_FSL_QSPI 280 #define CONFIG_SPI_FLASH_SPANSION 281 #endif 282 /* 283 * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure. 284 * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0 285 * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1 286 */ 287 #define FSL_QIXIS_BRDCFG9_QSPI 0x1 288 289 /* 290 * MMC 291 */ 292 #ifdef CONFIG_MMC 293 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ 294 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) 295 #endif 296 297 /* 298 * RTC configuration 299 */ 300 #define RTC 301 #define CONFIG_RTC_DS3231 1 302 #define CONFIG_RTC_ENABLE_32KHZ_OUTPUT 303 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 304 #define CONFIG_RTC_ENABLE_32KHZ_OUTPUT 305 306 /* EEPROM */ 307 #define CONFIG_ID_EEPROM 308 #define CONFIG_SYS_I2C_EEPROM_NXID 309 #define CONFIG_SYS_EEPROM_BUS_NUM 0 310 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 311 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 312 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 313 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 314 315 #define CONFIG_FSL_MEMAC 316 317 #ifdef CONFIG_PCI 318 #define CONFIG_PCI_SCAN_SHOW 319 #endif 320 321 /* MMC */ 322 #ifdef CONFIG_MMC 323 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 324 #endif 325 326 /* Initial environment variables */ 327 #undef CONFIG_EXTRA_ENV_SETTINGS 328 #ifdef CONFIG_NXP_ESBC 329 #define CONFIG_EXTRA_ENV_SETTINGS \ 330 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 331 "loadaddr=0x80100000\0" \ 332 "kernel_addr=0x100000\0" \ 333 "ramdisk_addr=0x800000\0" \ 334 "ramdisk_size=0x2000000\0" \ 335 "fdt_high=0xa0000000\0" \ 336 "initrd_high=0xffffffffffffffff\0" \ 337 "kernel_start=0x581000000\0" \ 338 "kernel_load=0xa0000000\0" \ 339 "kernel_size=0x2800000\0" \ 340 "mcmemsize=0x40000000\0" \ 341 "mcinitcmd=esbc_validate 0x580640000;" \ 342 "esbc_validate 0x580680000;" \ 343 "fsl_mc start mc 0x580a00000" \ 344 " 0x580e00000 \0" 345 #else 346 #ifdef CONFIG_TFABOOT 347 #define SD_MC_INIT_CMD \ 348 "mmcinfo;mmc read 0x80a00000 0x5000 0x1200;" \ 349 "mmc read 0x80e00000 0x7000 0x800;" \ 350 "fsl_mc start mc 0x80a00000 0x80e00000\0" 351 #define IFC_MC_INIT_CMD \ 352 "fsl_mc start mc 0x580a00000" \ 353 " 0x580e00000 \0" 354 #define CONFIG_EXTRA_ENV_SETTINGS \ 355 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 356 "loadaddr=0x80100000\0" \ 357 "loadaddr_sd=0x90100000\0" \ 358 "kernel_addr=0x581000000\0" \ 359 "kernel_addr_sd=0x8000\0" \ 360 "ramdisk_addr=0x800000\0" \ 361 "ramdisk_size=0x2000000\0" \ 362 "fdt_high=0xa0000000\0" \ 363 "initrd_high=0xffffffffffffffff\0" \ 364 "kernel_start=0x581000000\0" \ 365 "kernel_start_sd=0x8000\0" \ 366 "kernel_load=0xa0000000\0" \ 367 "kernel_size=0x2800000\0" \ 368 "kernel_size_sd=0x14000\0" \ 369 "load_addr=0xa0000000\0" \ 370 "kernelheader_addr=0x580600000\0" \ 371 "kernelheader_addr_r=0x80200000\0" \ 372 "kernelheader_size=0x40000\0" \ 373 "BOARD=ls2088aqds\0" \ 374 "mcmemsize=0x70000000 \0" \ 375 "scriptaddr=0x80000000\0" \ 376 "scripthdraddr=0x80080000\0" \ 377 IFC_MC_INIT_CMD \ 378 BOOTENV \ 379 "boot_scripts=ls2088aqds_boot.scr\0" \ 380 "boot_script_hdr=hdr_ls2088aqds_bs.out\0" \ 381 "scan_dev_for_boot_part=" \ 382 "part list ${devtype} ${devnum} devplist; " \ 383 "env exists devplist || setenv devplist 1; " \ 384 "for distro_bootpart in ${devplist}; do " \ 385 "if fstype ${devtype} " \ 386 "${devnum}:${distro_bootpart} " \ 387 "bootfstype; then " \ 388 "run scan_dev_for_boot; " \ 389 "fi; " \ 390 "done\0" \ 391 "boot_a_script=" \ 392 "load ${devtype} ${devnum}:${distro_bootpart} " \ 393 "${scriptaddr} ${prefix}${script}; " \ 394 "env exists secureboot && load ${devtype} " \ 395 "${devnum}:${distro_bootpart} " \ 396 "${scripthdraddr} ${prefix}${boot_script_hdr} " \ 397 "&& esbc_validate ${scripthdraddr};" \ 398 "source ${scriptaddr}\0" \ 399 "nor_bootcmd=echo Trying load from nor..;" \ 400 "cp.b $kernel_addr $load_addr " \ 401 "$kernel_size ; env exists secureboot && " \ 402 "cp.b $kernelheader_addr $kernelheader_addr_r " \ 403 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ 404 "bootm $load_addr#$BOARD\0" \ 405 "sd_bootcmd=echo Trying load from SD ..;" \ 406 "mmcinfo; mmc read $load_addr " \ 407 "$kernel_addr_sd $kernel_size_sd && " \ 408 "bootm $load_addr#$BOARD\0" 409 #elif defined(CONFIG_SD_BOOT) 410 #define CONFIG_EXTRA_ENV_SETTINGS \ 411 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 412 "loadaddr=0x90100000\0" \ 413 "kernel_addr=0x800\0" \ 414 "ramdisk_addr=0x800000\0" \ 415 "ramdisk_size=0x2000000\0" \ 416 "fdt_high=0xa0000000\0" \ 417 "initrd_high=0xffffffffffffffff\0" \ 418 "kernel_start=0x8000\0" \ 419 "kernel_load=0xa0000000\0" \ 420 "kernel_size=0x14000\0" \ 421 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ 422 "mmc read 0x80100000 0x7000 0x800;" \ 423 "fsl_mc start mc 0x80000000 0x80100000\0" \ 424 "mcmemsize=0x70000000 \0" 425 #else 426 #define CONFIG_EXTRA_ENV_SETTINGS \ 427 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 428 "loadaddr=0x80100000\0" \ 429 "kernel_addr=0x100000\0" \ 430 "ramdisk_addr=0x800000\0" \ 431 "ramdisk_size=0x2000000\0" \ 432 "fdt_high=0xa0000000\0" \ 433 "initrd_high=0xffffffffffffffff\0" \ 434 "kernel_start=0x581000000\0" \ 435 "kernel_load=0xa0000000\0" \ 436 "kernel_size=0x2800000\0" \ 437 "mcmemsize=0x40000000\0" \ 438 "mcinitcmd=fsl_mc start mc 0x580a00000" \ 439 " 0x580e00000 \0" 440 #endif /* CONFIG_TFABOOT */ 441 #endif /* CONFIG_NXP_ESBC */ 442 443 #ifdef CONFIG_TFABOOT 444 #define BOOT_TARGET_DEVICES(func) \ 445 func(USB, usb, 0) \ 446 func(MMC, mmc, 0) \ 447 func(SCSI, scsi, 0) \ 448 func(DHCP, dhcp, na) 449 #include <config_distro_bootcmd.h> 450 451 #define SD_BOOTCOMMAND \ 452 "env exists mcinitcmd && env exists secureboot "\ 453 "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \ 454 "&& esbc_validate $load_addr; " \ 455 "env exists mcinitcmd && run mcinitcmd " \ 456 "&& mmc read 0x80d00000 0x6800 0x800 " \ 457 "&& fsl_mc lazyapply dpl 0x80d00000; " \ 458 "run distro_bootcmd;run sd_bootcmd; " \ 459 "env exists secureboot && esbc_halt;" 460 461 #define IFC_NOR_BOOTCOMMAND \ 462 "env exists mcinitcmd && env exists secureboot "\ 463 "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\ 464 "&& fsl_mc lazyapply dpl 0x580d00000;" \ 465 "run distro_bootcmd;run nor_bootcmd; " \ 466 "env exists secureboot && esbc_halt;" 467 #endif 468 469 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) 470 #define CONFIG_FSL_MEMAC 471 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 472 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d 473 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 474 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 475 476 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 477 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 478 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 479 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 480 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 481 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 482 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 483 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 484 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 485 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 486 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa 487 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb 488 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc 489 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd 490 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe 491 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf 492 493 #define CONFIG_ETHPRIME "DPMAC1@xgmii" 494 495 #endif 496 497 #include <asm/fsl_secure_boot.h> 498 499 #endif /* __LS2_QDS_H */ 500