1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2019-2020
4  * Marvell <www.marvell.com>
5  */
6 
7 #ifndef __OCTEON_COMMON_H__
8 #define __OCTEON_COMMON_H__
9 
10 #if defined(CONFIG_RAM_OCTEON)
11 #define CONFIG_SYS_MALLOC_LEN		(16 << 20)
12 #define CONFIG_SYS_INIT_SP_OFFSET	0x20100000
13 #else
14 /* No DDR init -> run in L2 cache with limited resources */
15 #define CONFIG_SYS_MALLOC_LEN		(256 << 10)
16 #define CONFIG_SYS_INIT_SP_OFFSET	0x00180000
17 #endif
18 
19 #define CONFIG_SYS_SDRAM_BASE		0xffffffff80000000
20 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
21 
22 #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + (1 << 20))
23 
24 #define CONFIG_SYS_BOOTM_LEN		(64 << 20)	/* 64M */
25 
26 #endif /* __OCTEON_COMMON_H__ */
27