1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2018 NXP 4 */ 5 6 #ifndef __IMX8M_PICOPI_H 7 #define __IMX8M_PICOPI_H 8 9 #include <linux/sizes.h> 10 #include <asm/arch/imx-regs.h> 11 12 #define CONFIG_SPL_MAX_SIZE (124 * 1024) 13 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 14 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR 15 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 16 17 #ifdef CONFIG_SPL_BUILD 18 /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ 19 #define CONFIG_SPL_WATCHDOG_SUPPORT 20 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 21 #define CONFIG_SPL_POWER_SUPPORT 22 #define CONFIG_SPL_I2C_SUPPORT 23 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 24 #define CONFIG_SPL_STACK 0x187FF0 25 #define CONFIG_SPL_LIBCOMMON_SUPPORT 26 #define CONFIG_SPL_LIBGENERIC_SUPPORT 27 #define CONFIG_SPL_GPIO_SUPPORT 28 #define CONFIG_SPL_MMC_SUPPORT 29 #define CONFIG_SPL_BSS_START_ADDR 0x00180000 30 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ 31 #define CONFIG_SYS_SPL_MALLOC_START 0x42200000 32 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ 33 #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 34 35 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ 36 #define CONFIG_MALLOC_F_ADDR 0x182000 37 /* For RAW image gives a error info not panic */ 38 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE 39 40 #undef CONFIG_DM_MMC 41 #undef CONFIG_DM_PMIC 42 43 #define CONFIG_SYS_I2C 44 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 45 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 46 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 47 48 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 49 50 #define CONFIG_POWER 51 #define CONFIG_POWER_I2C 52 #endif 53 54 #define CONFIG_REMAKE_ELF 55 56 /* ENET Config */ 57 /* ENET1 */ 58 #if defined(CONFIG_CMD_NET) 59 #define CONFIG_MII 60 #define CONFIG_ETHPRIME "FEC" 61 62 #define CONFIG_FEC_MXC 63 #define CONFIG_FEC_XCV_TYPE RGMII 64 #define CONFIG_FEC_MXC_PHYADDR 1 65 #define FEC_QUIRK_ENET_MAC 66 67 #define CONFIG_PHY_GIGE 68 #define IMX_FEC_BASE 0x30BE0000 69 70 #define CONFIG_PHYLIB 71 #define CONFIG_PHY_ATHEROS 72 #endif 73 74 /* Initial environment variables */ 75 #define CONFIG_EXTRA_ENV_SETTINGS \ 76 "script=boot.scr\0" \ 77 "image=Image\0" \ 78 "console=ttymxc0,115200\0" \ 79 "fdt_addr=0x43000000\0" \ 80 "fdt_high=0xffffffffffffffff\0" \ 81 "fdt_file=imx8mq-pico-pi.dtb\0" \ 82 "initrd_addr=0x43800000\0" \ 83 "initrd_high=0xffffffffffffffff\0" \ 84 "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ 85 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ 86 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ 87 "mmcautodetect=yes\0" \ 88 "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ 89 "loadbootscript=" \ 90 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ 91 "bootscript=echo Running bootscript from mmc ...; source\0" \ 92 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ 93 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ 94 "mmcboot=echo Booting from mmc ...; " \ 95 "run mmcargs; " \ 96 "echo wait for boot; " \ 97 "fi;\0" \ 98 "netargs=setenv bootargs console=${console} " \ 99 "root=/dev/nfs " \ 100 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ 101 "netboot=echo Booting from net ...; " \ 102 "run netargs; " \ 103 "if test ${ip_dyn} = yes; then " \ 104 "setenv get_cmd dhcp; " \ 105 "else " \ 106 "setenv get_cmd tftp; " \ 107 "fi; " \ 108 "${get_cmd} ${loadaddr} ${image}; " \ 109 "booti; " 110 111 #define CONFIG_BOOTCOMMAND \ 112 "mmc dev ${mmcdev}; if mmc rescan; then " \ 113 "if run loadbootscript; then " \ 114 "run bootscript; " \ 115 "else " \ 116 "if run loadimage; then " \ 117 "run mmcboot; " \ 118 "else run netboot; " \ 119 "fi; " \ 120 "fi; " \ 121 "else booti ${loadaddr} - ${fdt_addr}; fi" 122 123 /* Link Definitions */ 124 #define CONFIG_LOADADDR 0x40480000 125 126 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 127 128 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 129 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 130 #define CONFIG_SYS_INIT_SP_OFFSET \ 131 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 132 #define CONFIG_SYS_INIT_SP_ADDR \ 133 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 134 135 #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ 136 137 /* Size of malloc() pool */ 138 #define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024) 139 140 #define CONFIG_SYS_SDRAM_BASE 0x40000000 141 #define PHYS_SDRAM 0x40000000 142 #define PHYS_SDRAM_SIZE 0x80000000 /* 2 GiB DDR */ 143 144 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM 145 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 146 (PHYS_SDRAM_SIZE >> 1)) 147 148 #define CONFIG_MXC_UART_BASE UART1_BASE_ADDR 149 150 /* Monitor Command Prompt */ 151 #define CONFIG_SYS_CBSIZE 1024 152 #define CONFIG_SYS_MAXARGS 64 153 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 154 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 155 sizeof(CONFIG_SYS_PROMPT) + 16) 156 157 #define CONFIG_IMX_BOOTAUX 158 159 #define CONFIG_SYS_FSL_USDHC_NUM 2 160 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 161 162 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 163 164 #define CONFIG_MXC_GPIO 165 166 /* I2C Configs */ 167 #define CONFIG_SYS_I2C_SPEED 100000 168 169 #define CONFIG_OF_SYSTEM_SETUP 170 171 #ifndef CONFIG_SPL_BUILD 172 #define CONFIG_DM_PMIC 173 #endif 174 175 #define CONFIG_SYS_BOOTM_LEN SZ_128M 176 177 #endif 178