1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2007-2008 4 * Stelian Pop <stelian@popies.net> 5 * Lead Tech Design <www.leadtechdesign.com> 6 * Ilko Iliev <www.ronetix.at> 7 * 8 * Configuation settings for the RONETIX PM9261 board. 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * SoC must be defined first, before hardware.h is included. 16 * In this case SoC is defined in boards.cfg. 17 */ 18 19 #include <asm/hardware.h> 20 /* ARM asynchronous clock */ 21 22 #define MASTER_PLL_DIV 15 23 #define MASTER_PLL_MUL 162 24 #define MAIN_PLL_DIV 2 25 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ 26 #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 27 28 #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261" 29 30 #define CONFIG_MACH_TYPE MACH_TYPE_PM9261 31 32 /* clocks */ 33 /* CKGR_MOR - enable main osc. */ 34 #define CONFIG_SYS_MOR_VAL \ 35 (AT91_PMC_MOR_MOSCEN | \ 36 (255 << 8)) /* Main Oscillator Start-up Time */ 37 #define CONFIG_SYS_PLLAR_VAL \ 38 (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \ 39 AT91_PMC_PLLXR_OUT(3) | \ 40 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) 41 42 /* PCK/2 = MCK Master Clock from PLLA */ 43 #define CONFIG_SYS_MCKR1_VAL \ 44 (AT91_PMC_MCKR_CSS_SLOW | \ 45 AT91_PMC_MCKR_PRES_1 | \ 46 AT91_PMC_MCKR_MDIV_2) 47 48 /* PCK/2 = MCK Master Clock from PLLA */ 49 #define CONFIG_SYS_MCKR2_VAL \ 50 (AT91_PMC_MCKR_CSS_PLLA | \ 51 AT91_PMC_MCKR_PRES_1 | \ 52 AT91_PMC_MCKR_MDIV_2) 53 54 /* define PDC[31:16] as DATA[31:16] */ 55 #define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000 56 /* no pull-up for D[31:16] */ 57 #define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000 58 59 /* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */ 60 #define CONFIG_SYS_MATRIX_EBICSA_VAL \ 61 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A) 62 63 /* SDRAM */ 64 /* SDRAMC_MR Mode register */ 65 #define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL 66 /* SDRAMC_TR - Refresh Timer register */ 67 #define CONFIG_SYS_SDRC_TR_VAL1 0x13C 68 /* SDRAMC_CR - Configuration register*/ 69 #define CONFIG_SYS_SDRC_CR_VAL \ 70 (AT91_SDRAMC_NC_9 | \ 71 AT91_SDRAMC_NR_13 | \ 72 AT91_SDRAMC_NB_4 | \ 73 AT91_SDRAMC_CAS_3 | \ 74 AT91_SDRAMC_DBW_32 | \ 75 (1 << 8) | /* Write Recovery Delay */ \ 76 (7 << 12) | /* Row Cycle Delay */ \ 77 (3 << 16) | /* Row Precharge Delay */ \ 78 (2 << 20) | /* Row to Column Delay */ \ 79 (5 << 24) | /* Active to Precharge Delay */ \ 80 (1 << 28)) /* Exit Self Refresh to Active Delay */ 81 82 /* Memory Device Register -> SDRAM */ 83 #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM 84 #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE 85 #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ 86 #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH 87 #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ 88 #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ 89 #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ 90 #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ 91 #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ 92 #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ 93 #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ 94 #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ 95 #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR 96 #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ 97 #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL 98 #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ 99 #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ 100 #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ 101 102 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ 103 #define CONFIG_SYS_SMC0_SETUP0_VAL \ 104 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ 105 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) 106 #define CONFIG_SYS_SMC0_PULSE0_VAL \ 107 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ 108 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) 109 #define CONFIG_SYS_SMC0_CYCLE0_VAL \ 110 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) 111 #define CONFIG_SYS_SMC0_MODE0_VAL \ 112 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ 113 AT91_SMC_MODE_DBW_16 | \ 114 AT91_SMC_MODE_TDF | \ 115 AT91_SMC_MODE_TDF_CYCLE(6)) 116 117 /* user reset enable */ 118 #define CONFIG_SYS_RSTC_RMR_VAL \ 119 (AT91_RSTC_KEY | \ 120 AT91_RSTC_CR_PROCRST | \ 121 AT91_RSTC_MR_ERSTL(1) | \ 122 AT91_RSTC_MR_ERSTL(2)) 123 124 /* Disable Watchdog */ 125 #define CONFIG_SYS_WDTC_WDMR_VAL \ 126 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ 127 AT91_WDT_MR_WDV(0xfff) | \ 128 AT91_WDT_MR_WDDIS | \ 129 AT91_WDT_MR_WDD(0xfff)) 130 131 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 132 #define CONFIG_SETUP_MEMORY_TAGS 1 133 #define CONFIG_INITRD_TAG 1 134 135 #undef CONFIG_SKIP_LOWLEVEL_INIT 136 137 /* 138 * Hardware drivers 139 */ 140 141 /* LCD */ 142 #define LCD_BPP LCD_COLOR8 143 #define CONFIG_LCD_LOGO 1 144 #undef LCD_TEST_PATTERN 145 #define CONFIG_LCD_INFO 1 146 #define CONFIG_LCD_INFO_BELOW_LOGO 1 147 #define CONFIG_ATMEL_LCD 1 148 #define CONFIG_ATMEL_LCD_BGR555 1 149 150 /* 151 * BOOTP options 152 */ 153 #define CONFIG_BOOTP_BOOTFILESIZE 1 154 155 /* SDRAM */ 156 #define PHYS_SDRAM 0x20000000 157 #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ 158 159 /* NAND flash */ 160 #define CONFIG_SYS_MAX_NAND_DEVICE 1 161 #define CONFIG_SYS_NAND_BASE 0x40000000 162 #define CONFIG_SYS_NAND_DBW_8 1 163 /* our ALE is AD22 */ 164 #define CONFIG_SYS_NAND_MASK_ALE (1 << 22) 165 /* our CLE is AD21 */ 166 #define CONFIG_SYS_NAND_MASK_CLE (1 << 21) 167 #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) 168 #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(16) 169 170 /* NOR flash */ 171 #define PHYS_FLASH_1 0x10000000 172 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 173 #define CONFIG_SYS_MAX_FLASH_SECT 256 174 #define CONFIG_SYS_MAX_FLASH_BANKS 1 175 176 /* Ethernet */ 177 #define CONFIG_DRIVER_DM9000 1 178 #define CONFIG_DM9000_BASE 0x30000000 179 #define DM9000_IO CONFIG_DM9000_BASE 180 #define DM9000_DATA (CONFIG_DM9000_BASE + 4) 181 #define CONFIG_DM9000_USE_16BIT 1 182 #define CONFIG_NET_RETRY_COUNT 20 183 #define CONFIG_RESET_PHY_R 1 184 185 /* USB */ 186 #define CONFIG_USB_ATMEL 187 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB 188 #define CONFIG_USB_OHCI_NEW 1 189 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 190 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 191 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261" 192 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 193 194 #define CONFIG_SYS_LOAD_ADDR 0x22000000 195 196 #undef CONFIG_SYS_USE_DATAFLASH_CS0 197 #undef CONFIG_SYS_USE_NANDFLASH 198 #define CONFIG_SYS_USE_FLASH 1 199 200 #ifdef CONFIG_SYS_USE_DATAFLASH_CS0 201 202 /* bootstrap + u-boot + env + linux in dataflash on CS0 */ 203 #define CONFIG_BOOTCOMMAND "sf probe 0; " \ 204 "sf read 0x22000000 0x84000 0x210000; " \ 205 "bootm 0x22000000" 206 207 #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CONFIG_SYS_USE_NANDFLASH */ 208 209 /* bootstrap + u-boot + env + linux in nandflash */ 210 #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" 211 212 #elif defined (CONFIG_SYS_USE_FLASH) 213 /* JFFS Partition offset set */ 214 #define CONFIG_SYS_JFFS2_FIRST_BANK 0 215 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 216 217 /* 512k reserved for u-boot */ 218 #define CONFIG_SYS_JFFS2_FIRST_SECTOR 11 219 220 #define CONFIG_BOOTCOMMAND "run flashboot" 221 222 #define CONFIG_CON_ROT "fbcon=rotate:3 " 223 224 #define CONFIG_EXTRA_ENV_SETTINGS \ 225 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ 226 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ 227 "partition=nand0,0\0" \ 228 "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ 229 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 230 CONFIG_CON_ROT \ 231 "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \ 232 "addip=setenv bootargs $(bootargs) " \ 233 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\ 234 ":$(hostname):eth0:off\0" \ 235 "ramboot=tftpboot 0x22000000 vmImage;" \ 236 "run ramargs;run addip;bootm 22000000\0" \ 237 "nfsboot=tftpboot 0x22000000 vmImage;" \ 238 "run nfsargs;run addip;bootm 22000000\0" \ 239 "flashboot=run ramargs;run addip;bootm 0x10050000\0" \ 240 "" 241 #else 242 #error "Undefined memory device" 243 #endif 244 245 /* 246 * Size of malloc() pool 247 */ 248 #define CONFIG_SYS_MALLOC_LEN \ 249 ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) 250 251 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 252 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - \ 253 GENERATED_GBL_DATA_SIZE) 254 255 #endif 256