1 #ifndef __CONFIG_H 2 #define __CONFIG_H 3 4 #define CONFIG_CPU_SH7751 1 5 #define __LITTLE_ENDIAN__ 1 6 7 #define CONFIG_DISPLAY_BOARDINFO 8 9 /* SCIF */ 10 #define CONFIG_CONS_SCIF1 1 11 12 /* SDRAM */ 13 #define CONFIG_SYS_SDRAM_BASE 0x8C000000 14 #define CONFIG_SYS_SDRAM_SIZE 0x04000000 15 16 #define CONFIG_SYS_PBSIZE 256 17 18 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) 19 /* Address of u-boot image in Flash */ 20 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) 21 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 22 /* Size of DRAM reserved for malloc() use */ 23 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 24 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 25 26 /* 27 * NOR Flash ( Spantion S29GL256P ) 28 */ 29 #define CONFIG_SYS_FLASH_BASE (0xA0000000) 30 #define CONFIG_SYS_MAX_FLASH_BANKS (1) 31 #define CONFIG_SYS_MAX_FLASH_SECT 256 32 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 33 34 /* 35 * SuperH Clock setting 36 */ 37 #define CONFIG_SYS_CLK_FREQ 60000000 38 #define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */ 39 40 /* 41 * IDE support 42 */ 43 #define CONFIG_IDE_RESET 1 44 #define CONFIG_SYS_PIO_MODE 1 45 #define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */ 46 #define CONFIG_SYS_IDE_MAXDEVICE 1 47 #define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000 48 #define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */ 49 #define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */ 50 #define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */ 51 #define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */ 52 #define CONFIG_IDE_SWAP_IO 53 54 /* 55 * SuperH PCI Bridge Configration 56 */ 57 #define CONFIG_SH7751_PCI 58 59 #endif /* __CONFIG_H */ 60