1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2007 Wind River Systems <www.windriver.com> 4 * Copyright 2007 Embedded Specialties, Inc. 5 * Joe Hamman <joe.hamman@embeddedspecialties.com> 6 * 7 * Copyright 2006 Freescale Semiconductor. 8 * 9 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 10 */ 11 12 /* 13 * SBC8641D board configuration file 14 * 15 * Make sure you change the MAC address and other network params first, 16 * search for CONFIG_SERVERIP, etc in this file. 17 */ 18 19 #ifndef __CONFIG_H 20 #define __CONFIG_H 21 22 /* High Level Configuration Options */ 23 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 24 25 #ifdef RUN_DIAG 26 #define CONFIG_SYS_DIAG_ADDR 0xff800000 27 #endif 28 29 #define CONFIG_SYS_RESET_ADDRESS 0xfff00100 30 31 /* 32 * virtual address to be used for temporary mappings. There 33 * should be 128k free at this VA. 34 */ 35 #define CONFIG_SYS_SCRATCH_VA 0xe8000000 36 37 #define CONFIG_SYS_SRIO 38 #define CONFIG_SRIO1 /* SRIO port 1 */ 39 40 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ 41 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ 42 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 43 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 44 45 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ 46 47 #undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/ 48 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 49 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 50 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 51 #define CACHE_LINE_INTERLEAVING 0x20000000 52 #define PAGE_INTERLEAVING 0x21000000 53 #define BANK_INTERLEAVING 0x22000000 54 #define SUPER_BANK_INTERLEAVING 0x23000000 55 56 #define CONFIG_ALTIVEC 1 57 58 /* 59 * L2CR setup -- make sure this is right for your board! 60 */ 61 #define CONFIG_SYS_L2 62 #define L2_INIT 0 63 #define L2_ENABLE (L2CR_L2E) 64 65 #ifndef CONFIG_SYS_CLK_FREQ 66 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 67 #endif 68 69 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 70 71 /* 72 * Base addresses -- Note these are effective addresses where the 73 * actual resources get mapped (not physical addresses) 74 */ 75 #define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ 76 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 77 78 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 79 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 80 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW 81 82 /* 83 * DDR Setup 84 */ 85 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ 86 #define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */ 87 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 88 #define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2 89 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 90 #define CONFIG_VERY_BIG_RAM 91 92 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 93 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 94 95 #if defined(CONFIG_SPD_EEPROM) 96 /* 97 * Determine DDR configuration from I2C interface. 98 */ 99 #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ 100 #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ 101 #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ 102 #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ 103 104 #else 105 /* 106 * Manually set up DDR1 & DDR2 parameters 107 */ 108 109 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 110 111 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 112 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 113 #define CONFIG_SYS_DDR_CS2_BNDS 0x00000000 114 #define CONFIG_SYS_DDR_CS3_BNDS 0x00000000 115 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 116 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 117 #define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000 118 #define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000 119 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 120 #define CONFIG_SYS_DDR_TIMING_0 0x00220802 121 #define CONFIG_SYS_DDR_TIMING_1 0x38377322 122 #define CONFIG_SYS_DDR_TIMING_2 0x002040c7 123 #define CONFIG_SYS_DDR_CFG_1A 0x43008008 124 #define CONFIG_SYS_DDR_CFG_2 0x24401000 125 #define CONFIG_SYS_DDR_MODE_1 0x23c00542 126 #define CONFIG_SYS_DDR_MODE_2 0x00000000 127 #define CONFIG_SYS_DDR_MODE_CTL 0x00000000 128 #define CONFIG_SYS_DDR_INTERVAL 0x05080100 129 #define CONFIG_SYS_DDR_DATA_INIT 0x00000000 130 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 131 #define CONFIG_SYS_DDR_CFG_1B 0xC3008008 132 133 #define CONFIG_SYS_DDR2_CS0_BNDS 0x0010001F 134 #define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000 135 #define CONFIG_SYS_DDR2_CS2_BNDS 0x00000000 136 #define CONFIG_SYS_DDR2_CS3_BNDS 0x00000000 137 #define CONFIG_SYS_DDR2_CS0_CONFIG 0x80010102 138 #define CONFIG_SYS_DDR2_CS1_CONFIG 0x00000000 139 #define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000 140 #define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000 141 #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000 142 #define CONFIG_SYS_DDR2_TIMING_0 0x00220802 143 #define CONFIG_SYS_DDR2_TIMING_1 0x38377322 144 #define CONFIG_SYS_DDR2_TIMING_2 0x002040c7 145 #define CONFIG_SYS_DDR2_CFG_1A 0x43008008 146 #define CONFIG_SYS_DDR2_CFG_2 0x24401000 147 #define CONFIG_SYS_DDR2_MODE_1 0x23c00542 148 #define CONFIG_SYS_DDR2_MODE_2 0x00000000 149 #define CONFIG_SYS_DDR2_MODE_CTL 0x00000000 150 #define CONFIG_SYS_DDR2_INTERVAL 0x05080100 151 #define CONFIG_SYS_DDR2_DATA_INIT 0x00000000 152 #define CONFIG_SYS_DDR2_CLK_CTRL 0x03800000 153 #define CONFIG_SYS_DDR2_CFG_1B 0xC3008008 154 155 #endif 156 157 /* #define CONFIG_ID_EEPROM 1 158 #define ID_EEPROM_ADDR 0x57 */ 159 160 /* 161 * The SBC8641D contains 16MB flash space at ff000000. 162 */ 163 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 164 165 /* Flash */ 166 #define CONFIG_SYS_BR0_PRELIM 0xff001001 /* port size 16bit */ 167 #define CONFIG_SYS_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */ 168 169 /* 64KB EEPROM */ 170 #define CONFIG_SYS_BR1_PRELIM 0xf0000801 /* port size 16bit */ 171 #define CONFIG_SYS_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */ 172 173 /* EPLD - User switches, board id, LEDs */ 174 #define CONFIG_SYS_BR2_PRELIM 0xf1000801 /* port size 16bit */ 175 #define CONFIG_SYS_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */ 176 177 /* Local bus SDRAM 128MB */ 178 #define CONFIG_SYS_BR3_PRELIM 0xe0001861 /* port size ?bit */ 179 #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */ 180 #define CONFIG_SYS_BR4_PRELIM 0xe4001861 /* port size ?bit */ 181 #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */ 182 183 /* Disk on Chip (DOC) 128MB */ 184 #define CONFIG_SYS_BR5_PRELIM 0xe8001001 /* port size ?bit */ 185 #define CONFIG_SYS_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */ 186 187 /* LCD */ 188 #define CONFIG_SYS_BR6_PRELIM 0xf4000801 /* port size ?bit */ 189 #define CONFIG_SYS_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ 190 191 /* Control logic & misc peripherals */ 192 #define CONFIG_SYS_BR7_PRELIM 0xf2000801 /* port size ?bit */ 193 #define CONFIG_SYS_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ 194 195 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 196 #define CONFIG_SYS_MAX_FLASH_SECT 131 /* sectors per device */ 197 198 #undef CONFIG_SYS_FLASH_CHECKSUM 199 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 200 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 201 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 202 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 203 204 #define CONFIG_SYS_WRITE_SWAPPED_DATA 205 #define CONFIG_SYS_FLASH_EMPTY_INFO 206 207 #define CONFIG_SYS_INIT_RAM_LOCK 1 208 #ifndef CONFIG_SYS_INIT_RAM_LOCK 209 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ 210 #else 211 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ 212 #endif 213 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 214 215 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 216 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 217 218 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 219 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 220 221 /* Serial Port */ 222 #define CONFIG_SYS_NS16550_SERIAL 223 #define CONFIG_SYS_NS16550_REG_SIZE 1 224 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 225 226 #define CONFIG_SYS_BAUDRATE_TABLE \ 227 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 228 229 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 230 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 231 232 /* 233 * I2C 234 */ 235 #define CONFIG_SYS_I2C 236 #define CONFIG_SYS_I2C_FSL 237 #define CONFIG_SYS_FSL_I2C_SPEED 400000 238 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 239 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 240 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 241 242 /* 243 * RapidIO MMU 244 */ 245 #define CONFIG_SYS_SRIO1_MEM_BASE 0xc0000000 /* base address */ 246 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE 247 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */ 248 249 /* 250 * General PCI 251 * Addresses are mapped 1-1. 252 */ 253 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 254 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS 255 #define CONFIG_SYS_PCIE1_MEM_VIRT CONFIG_SYS_PCIE1_MEM_BUS 256 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 257 #define CONFIG_SYS_PCIE1_IO_BUS 0xe2000000 258 #define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS 259 #define CONFIG_SYS_PCIE1_IO_VIRT CONFIG_SYS_PCIE1_IO_BUS 260 #define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */ 261 262 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 263 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS 264 #define CONFIG_SYS_PCIE2_MEM_VIRT CONFIG_SYS_PCIE2_MEM_BUS 265 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 266 #define CONFIG_SYS_PCIE2_IO_BUS 0xe3000000 267 #define CONFIG_SYS_PCIE2_IO_PHYS CONFIG_SYS_PCIE2_IO_BUS 268 #define CONFIG_SYS_PCIE2_IO_VIRT CONFIG_SYS_PCIE2_IO_BUS 269 #define CONFIG_SYS_PCIE2_IO_SIZE 0x1000000 /* 16M */ 270 271 #if defined(CONFIG_PCI) 272 273 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 274 275 276 #if !defined(CONFIG_PCI_PNP) 277 #define PCI_ENET0_IOADDR 0xe0000000 278 #define PCI_ENET0_MEMADDR 0xe0000000 279 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 280 #endif 281 282 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 283 284 #ifdef CONFIG_SCSI_AHCI 285 #define CONFIG_SATA_ULI5288 286 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 287 #define CONFIG_SYS_SCSI_MAX_LUN 1 288 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 289 #endif 290 291 #endif /* CONFIG_PCI */ 292 293 #if defined(CONFIG_TSEC_ENET) 294 #define CONFIG_TSEC1 1 295 #define CONFIG_TSEC1_NAME "eTSEC1" 296 #define CONFIG_TSEC2 1 297 #define CONFIG_TSEC2_NAME "eTSEC2" 298 #define CONFIG_TSEC3 1 299 #define CONFIG_TSEC3_NAME "eTSEC3" 300 #define CONFIG_TSEC4 1 301 #define CONFIG_TSEC4_NAME "eTSEC4" 302 303 #define TSEC1_PHY_ADDR 0x1F 304 #define TSEC2_PHY_ADDR 0x00 305 #define TSEC3_PHY_ADDR 0x01 306 #define TSEC4_PHY_ADDR 0x02 307 #define TSEC1_PHYIDX 0 308 #define TSEC2_PHYIDX 0 309 #define TSEC3_PHYIDX 0 310 #define TSEC4_PHYIDX 0 311 #define TSEC1_FLAGS TSEC_GIGABIT 312 #define TSEC2_FLAGS TSEC_GIGABIT 313 #define TSEC3_FLAGS TSEC_GIGABIT 314 #define TSEC4_FLAGS TSEC_GIGABIT 315 316 #define CONFIG_SYS_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */ 317 318 #define CONFIG_ETHPRIME "eTSEC1" 319 320 #endif /* CONFIG_TSEC_ENET */ 321 322 /* 323 * BAT0 2G Cacheable, non-guarded 324 * 0x0000_0000 2G DDR 325 */ 326 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 327 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) 328 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) 329 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U 330 331 /* 332 * BAT1 1G Cache-inhibited, guarded 333 * 0x8000_0000 512M PCI-Express 1 Memory 334 * 0xa000_0000 512M PCI-Express 2 Memory 335 * Changed it for operating from 0xd0000000 336 */ 337 #define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \ 338 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 339 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP) 340 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 341 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 342 343 /* 344 * BAT2 512M Cache-inhibited, guarded 345 * 0xc000_0000 512M RapidIO Memory 346 */ 347 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \ 348 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 349 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) 350 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 351 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 352 353 /* 354 * BAT3 4M Cache-inhibited, guarded 355 * 0xf800_0000 4M CCSR 356 */ 357 #define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \ 358 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 359 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) 360 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 361 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 362 363 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 364 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 365 | BATL_PP_RW | BATL_CACHEINHIBIT \ 366 | BATL_GUARDEDSTORAGE) 367 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ 368 | BATU_BL_1M | BATU_VS | BATU_VP) 369 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 370 | BATL_PP_RW | BATL_CACHEINHIBIT) 371 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 372 #endif 373 374 /* 375 * BAT4 32M Cache-inhibited, guarded 376 * 0xe200_0000 16M PCI-Express 1 I/O 377 * 0xe300_0000 16M PCI-Express 2 I/0 378 * Note that this is at 0xe0000000 379 */ 380 #define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \ 381 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 382 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP) 383 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 384 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 385 386 /* 387 * BAT5 128K Cacheable, non-guarded 388 * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) 389 */ 390 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 391 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 392 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 393 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 394 395 /* 396 * BAT6 32M Cache-inhibited, guarded 397 * 0xfe00_0000 32M FLASH 398 */ 399 #define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ 400 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 401 #define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) 402 #define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) 403 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 404 405 /* Map the last 1M of flash where we're running from reset */ 406 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 407 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 408 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 409 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 410 | BATL_MEMCOHERENCE) 411 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 412 413 #define CONFIG_SYS_DBAT7L 0x00000000 414 #define CONFIG_SYS_DBAT7U 0x00000000 415 #define CONFIG_SYS_IBAT7L 0x00000000 416 #define CONFIG_SYS_IBAT7U 0x00000000 417 418 /* 419 * Environment 420 */ 421 422 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 423 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 424 425 #undef CONFIG_WATCHDOG /* watchdog disabled */ 426 427 /* 428 * Miscellaneous configurable options 429 */ 430 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 431 432 /* 433 * For booting Linux, the board info and command line data 434 * have to be in the first 8 MB of memory, since this is 435 * the maximum mapped by the Linux kernel during initialization. 436 */ 437 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 438 439 /* Cache Configuration */ 440 #define CONFIG_SYS_DCACHE_SIZE 32768 441 #define CONFIG_SYS_CACHELINE_SIZE 32 442 #if defined(CONFIG_CMD_KGDB) 443 #define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 444 #endif 445 446 #if defined(CONFIG_CMD_KGDB) 447 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 448 #endif 449 450 /* 451 * Environment Configuration 452 */ 453 454 #define CONFIG_HAS_ETH0 1 455 #define CONFIG_HAS_ETH1 1 456 #define CONFIG_HAS_ETH2 1 457 #define CONFIG_HAS_ETH3 1 458 459 #define CONFIG_IPADDR 192.168.0.50 460 461 #define CONFIG_HOSTNAME "sbc8641d" 462 #define CONFIG_ROOTPATH "/opt/eldk/ppc_74xx" 463 #define CONFIG_BOOTFILE "uImage" 464 465 #define CONFIG_SERVERIP 192.168.0.2 466 #define CONFIG_GATEWAYIP 192.168.0.1 467 #define CONFIG_NETMASK 255.255.255.0 468 469 /* default location for tftp and bootm */ 470 #define CONFIG_LOADADDR 1000000 471 472 #define CONFIG_EXTRA_ENV_SETTINGS \ 473 "netdev=eth0\0" \ 474 "consoledev=ttyS0\0" \ 475 "ramdiskaddr=2000000\0" \ 476 "ramdiskfile=uRamdisk\0" \ 477 "dtbaddr=400000\0" \ 478 "dtbfile=sbc8641d.dtb\0" \ 479 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 480 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 481 "maxcpus=1" 482 483 #define CONFIG_NFSBOOTCOMMAND \ 484 "setenv bootargs root=/dev/nfs rw " \ 485 "nfsroot=$serverip:$rootpath " \ 486 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 487 "console=$consoledev,$baudrate $othbootargs;" \ 488 "tftp $loadaddr $bootfile;" \ 489 "tftp $dtbaddr $dtbfile;" \ 490 "bootm $loadaddr - $dtbaddr" 491 492 #define CONFIG_RAMBOOTCOMMAND \ 493 "setenv bootargs root=/dev/ram rw " \ 494 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 495 "console=$consoledev,$baudrate $othbootargs;" \ 496 "tftp $ramdiskaddr $ramdiskfile;" \ 497 "tftp $loadaddr $bootfile;" \ 498 "tftp $dtbaddr $dtbfile;" \ 499 "bootm $loadaddr $ramdiskaddr $dtbaddr" 500 501 #define CONFIG_FLASHBOOTCOMMAND \ 502 "setenv bootargs root=/dev/ram rw " \ 503 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 504 "console=$consoledev,$baudrate $othbootargs;" \ 505 "bootm ffd00000 ffb00000 ffa00000" 506 507 #define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND 508 509 #endif /* __CONFIG_H */ 510