1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2012 Altera Corporation <www.altera.com> 4 */ 5 #ifndef __CONFIG_SOCFPGA_COMMON_H__ 6 #define __CONFIG_SOCFPGA_COMMON_H__ 7 8 #include <linux/stringify.h> 9 10 /* 11 * High level configuration 12 */ 13 #define CONFIG_CLOCKS 14 15 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 16 17 /* 18 * Memory configurations 19 */ 20 #define PHYS_SDRAM_1 0x0 21 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) 22 #if defined(CONFIG_TARGET_SOCFPGA_GEN5) 23 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 24 #define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE 25 #define CONFIG_SPL_PAD_TO 0x10000 26 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 27 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 28 #define CONFIG_SPL_PAD_TO 0x40000 29 /* SPL memory allocation configuration, this is for FAT implementation */ 30 #ifndef CONFIG_SYS_SPL_MALLOC_SIZE 31 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000 32 #endif 33 #define CONFIG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \ 34 CONFIG_SYS_SPL_MALLOC_SIZE) 35 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_ADDR + \ 36 CONFIG_SYS_INIT_RAM_SIZE) 37 #endif 38 39 /* 40 * Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal 41 * SRAM as bootcounter storage. Make sure to not put the stack directly 42 * at this address to not overwrite the bootcounter by checking, if the 43 * bootcounter address is located in the internal SRAM. 44 */ 45 #if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \ 46 (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \ 47 CONFIG_SYS_INIT_RAM_SIZE))) 48 #define CONFIG_SPL_STACK CONFIG_SYS_BOOTCOUNT_ADDR 49 #else 50 #define CONFIG_SPL_STACK \ 51 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) 52 #endif 53 54 /* 55 * U-Boot stack setup: if SPL post-reloc uses DDR stack, use it in pre-reloc 56 * phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage 57 * in U-Boot pre-reloc is higher than in SPL. 58 */ 59 #if defined(CONFIG_SPL_STACK_R_ADDR) && CONFIG_SPL_STACK_R_ADDR 60 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK_R_ADDR 61 #else 62 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK 63 #endif 64 65 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 66 67 /* 68 * U-Boot general configurations 69 */ 70 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ 71 /* Print buffer size */ 72 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ 73 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 74 /* Boot argument buffer size */ 75 76 /* 77 * Cache 78 */ 79 #define CONFIG_SYS_L2_PL310 80 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS 81 82 /* 83 * Ethernet on SoC (EMAC) 84 */ 85 #ifdef CONFIG_CMD_NET 86 #define CONFIG_DW_ALTDESCRIPTOR 87 #endif 88 89 /* 90 * FPGA Driver 91 */ 92 #ifdef CONFIG_CMD_FPGA 93 #define CONFIG_FPGA_COUNT 1 94 #endif 95 96 /* 97 * L4 OSC1 Timer 0 98 */ 99 #ifndef CONFIG_TIMER 100 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS 101 #define CONFIG_SYS_TIMER_COUNTS_DOWN 102 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) 103 #ifndef CONFIG_SYS_TIMER_RATE 104 #define CONFIG_SYS_TIMER_RATE 25000000 105 #endif 106 #endif 107 108 /* 109 * L4 Watchdog 110 */ 111 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS 112 #define CONFIG_DW_WDT_CLOCK_KHZ 25000 113 114 /* 115 * MMC Driver 116 */ 117 #ifdef CONFIG_CMD_MMC 118 /* FIXME */ 119 /* using smaller max blk cnt to avoid flooding the limited stack we have */ 120 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ 121 #endif 122 123 /* 124 * NAND Support 125 */ 126 #ifdef CONFIG_NAND_DENALI 127 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 128 #define CONFIG_SYS_MAX_NAND_DEVICE 1 129 #define CONFIG_SYS_NAND_ONFI_DETECTION 130 #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS 131 #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS 132 #endif 133 134 /* 135 * QSPI support 136 */ 137 /* QSPI reference clock */ 138 #ifndef __ASSEMBLY__ 139 unsigned int cm_get_qspi_controller_clk_hz(void); 140 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() 141 #endif 142 143 /* 144 * USB 145 */ 146 147 /* 148 * USB Gadget (DFU, UMS) 149 */ 150 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) 151 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024) 152 #define DFU_DEFAULT_POLL_TIMEOUT 300 153 154 /* USB IDs */ 155 #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 156 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 157 #endif 158 159 /* 160 * U-Boot environment 161 */ 162 163 /* Environment for SDMMC boot */ 164 165 /* Environment for QSPI boot */ 166 167 /* 168 * SPL 169 * 170 * SRAM Memory layout for gen 5: 171 * 172 * 0xFFFF_0000 ...... Start of SRAM 173 * 0xFFFF_xxxx ...... Top of stack (grows down) 174 * 0xFFFF_yyyy ...... Global Data 175 * 0xFFFF_zzzz ...... Malloc area 176 * 0xFFFF_FFFF ...... End of SRAM 177 * 178 * SRAM Memory layout for Arria 10: 179 * 0xFFE0_0000 ...... Start of SRAM (bottom) 180 * 0xFFEx_xxxx ...... Top of stack (grows down to bottom) 181 * 0xFFEy_yyyy ...... Global Data 182 * 0xFFEz_zzzz ...... Malloc area (grows up to top) 183 * 0xFFE3_FFFF ...... End of SRAM (top) 184 */ 185 #ifndef CONFIG_SPL_TEXT_BASE 186 #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE 187 #endif 188 189 /* SPL SDMMC boot support */ 190 #ifdef CONFIG_SPL_MMC_SUPPORT 191 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) 192 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 193 #endif 194 #else 195 #ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 196 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 197 #endif 198 #endif 199 200 /* SPL QSPI boot support */ 201 202 /* SPL NAND boot support */ 203 #ifdef CONFIG_SPL_NAND_SUPPORT 204 #if defined(CONFIG_TARGET_SOCFPGA_GEN5) 205 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 206 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 207 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x100000 208 #endif 209 #endif 210 211 /* Extra Environment */ 212 #ifndef CONFIG_SPL_BUILD 213 214 #ifdef CONFIG_CMD_DHCP 215 #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) 216 #else 217 #define BOOT_TARGET_DEVICES_DHCP(func) 218 #endif 219 220 #if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP) 221 #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) 222 #else 223 #define BOOT_TARGET_DEVICES_PXE(func) 224 #endif 225 226 #ifdef CONFIG_CMD_MMC 227 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) 228 #else 229 #define BOOT_TARGET_DEVICES_MMC(func) 230 #endif 231 232 #define BOOT_TARGET_DEVICES(func) \ 233 BOOT_TARGET_DEVICES_MMC(func) \ 234 BOOT_TARGET_DEVICES_PXE(func) \ 235 BOOT_TARGET_DEVICES_DHCP(func) 236 237 #include <config_distro_bootcmd.h> 238 239 #ifndef CONFIG_EXTRA_ENV_SETTINGS 240 #define CONFIG_EXTRA_ENV_SETTINGS \ 241 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ 242 "bootm_size=0xa000000\0" \ 243 "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ 244 "fdt_addr_r=0x02000000\0" \ 245 "scriptaddr=0x02100000\0" \ 246 "pxefile_addr_r=0x02200000\0" \ 247 "ramdisk_addr_r=0x02300000\0" \ 248 "socfpga_legacy_reset_compat=1\0" \ 249 BOOTENV 250 251 #endif 252 #endif 253 254 #endif /* __CONFIG_SOCFPGA_COMMON_H__ */ 255