1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> 4 */ 5 6 #ifndef _CONFIG_THEADORABLE_H 7 #define _CONFIG_THEADORABLE_H 8 9 /* 10 * High Level Configuration Options (easy to change) 11 */ 12 13 /* 14 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 15 * for DDR ECC byte filling in the SPL before loading the main 16 * U-Boot into it. 17 */ 18 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 19 20 /* 21 * The debugging version enables USB support via defconfig. 22 * This version should also enable all other non-production 23 * interfaces / features. 24 */ 25 26 /* I2C */ 27 #define CONFIG_SYS_I2C 28 #define CONFIG_SYS_I2C_MVTWSI 29 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 30 #define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE 31 #define CONFIG_SYS_I2C_SLAVE 0x0 32 #define CONFIG_SYS_I2C_SPEED 100000 33 34 /* USB/EHCI configuration */ 35 #define CONFIG_EHCI_IS_TDI 36 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 37 38 /* Environment in SPI NOR flash */ 39 40 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 41 42 /* Keep device tree and initrd in lower memory so the kernel can access them */ 43 #define CONFIG_EXTRA_ENV_SETTINGS \ 44 "fdt_high=0x10000000\0" \ 45 "initrd_high=0x10000000\0" 46 47 /* SATA support */ 48 #define CONFIG_SYS_SATA_MAX_DEVICE 1 49 #define CONFIG_LBA48 50 51 /* Enable LCD and reserve 512KB from top of memory*/ 52 #define CONFIG_SYS_MEM_TOP_HIDE 0x80000 53 54 /* FPGA programming support */ 55 #define CONFIG_FPGA_STRATIX_V 56 57 /* 58 * Bootcounter 59 */ 60 /* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */ 61 #define BOOTCOUNT_ADDR 0x1000 62 63 /* 64 * mv-common.h should be defined after CMD configs since it used them 65 * to enable certain macros 66 */ 67 #include "mv-common.h" 68 69 /* 70 * Memory layout while starting into the bin_hdr via the 71 * BootROM: 72 * 73 * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 74 * 0x4000.4030 bin_hdr start address 75 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 76 * 0x4007.fffc BootROM stack top 77 * 78 * The address space between 0x4007.fffc and 0x400f.fff is not locked in 79 * L2 cache thus cannot be used. 80 */ 81 82 /* SPL */ 83 /* Defines for SPL */ 84 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 85 86 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 87 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 88 89 #ifdef CONFIG_SPL_BUILD 90 #define CONFIG_SYS_MALLOC_SIMPLE 91 #endif 92 93 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 94 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 95 96 /* SPL related SPI defines */ 97 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS 98 99 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ 100 #define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */ 101 102 #endif /* _CONFIG_THEADORABLE_H */ 103