1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Configuration for Versatile Express. Parts were derived from other ARM 4 * configurations. 5 */ 6 7 #ifndef __VEXPRESS_AEMV8A_H 8 #define __VEXPRESS_AEMV8A_H 9 10 #define CONFIG_REMAKE_ELF 11 12 /* Link Definitions */ 13 #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP 14 /* ATF loads u-boot here for BASE_FVP model */ 15 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) 16 #elif CONFIG_TARGET_VEXPRESS64_JUNO 17 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) 18 #endif 19 20 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 21 22 /* CS register bases for the original memory map. */ 23 #define V2M_PA_CS0 0x00000000 24 #define V2M_PA_CS1 0x14000000 25 #define V2M_PA_CS2 0x18000000 26 #define V2M_PA_CS3 0x1c000000 27 #define V2M_PA_CS4 0x0c000000 28 #define V2M_PA_CS5 0x10000000 29 30 #define V2M_PERIPH_OFFSET(x) (x << 16) 31 #define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1)) 32 #define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2)) 33 #define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3)) 34 35 #define V2M_BASE 0x80000000 36 37 /* Common peripherals relative to CS7. */ 38 #define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4)) 39 #define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5)) 40 #define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6)) 41 #define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7)) 42 43 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO 44 #define V2M_UART0 0x7ff80000 45 #define V2M_UART1 0x7ff70000 46 #else /* Not Juno */ 47 #define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9)) 48 #define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10)) 49 #define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11)) 50 #define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12)) 51 #endif 52 53 #define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15)) 54 55 #define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17)) 56 #define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18)) 57 58 #define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22)) 59 #define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23)) 60 61 #define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26)) 62 63 #define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31)) 64 65 /* System register offsets. */ 66 #define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0) 67 #define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4) 68 #define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8) 69 70 /* Generic Timer Definitions */ 71 #define COUNTER_FREQUENCY 24000000 /* 24MHz */ 72 73 /* Generic Interrupt Controller Definitions */ 74 #ifdef CONFIG_GICV3 75 #define GICD_BASE (0x2f000000) 76 #define GICR_BASE (0x2f100000) 77 #else 78 79 #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP 80 #define GICD_BASE (0x2f000000) 81 #define GICC_BASE (0x2c000000) 82 #elif CONFIG_TARGET_VEXPRESS64_JUNO 83 #define GICD_BASE (0x2C010000) 84 #define GICC_BASE (0x2C02f000) 85 #endif 86 #endif /* !CONFIG_GICV3 */ 87 88 /* Size of malloc() pool */ 89 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) 90 91 #ifndef CONFIG_TARGET_VEXPRESS64_JUNO 92 /* The Vexpress64 simulators use SMSC91C111 */ 93 #define CONFIG_SMC91111 1 94 #define CONFIG_SMC91111_BASE (0x01A000000) 95 #endif 96 97 /* PL011 Serial Configuration */ 98 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO 99 #define CONFIG_PL011_CLOCK 7372800 100 #else 101 #define CONFIG_PL011_CLOCK 24000000 102 #endif 103 104 /* BOOTP options */ 105 #define CONFIG_BOOTP_BOOTFILESIZE 106 107 /* Miscellaneous configurable options */ 108 #define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000) 109 110 /* Physical Memory Map */ 111 #define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ 112 /* Top 16MB reserved for secure world use */ 113 #define DRAM_SEC_SIZE 0x01000000 114 #define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE 115 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 116 117 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO 118 #define PHYS_SDRAM_2 (0x880000000) 119 #define PHYS_SDRAM_2_SIZE 0x180000000 120 #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP && CONFIG_NR_DRAM_BANKS == 2 121 #define PHYS_SDRAM_2 (0x880000000) 122 #define PHYS_SDRAM_2_SIZE 0x80000000 123 #endif 124 125 /* Enable memtest */ 126 127 /* Initial environment variables */ 128 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO 129 /* 130 * Defines where the kernel and FDT exist in NOR flash and where it will 131 * be copied into DRAM 132 */ 133 #define CONFIG_EXTRA_ENV_SETTINGS \ 134 "kernel_name=norkern\0" \ 135 "kernel_alt_name=Image\0" \ 136 "kernel_addr_r=0x80080000\0" \ 137 "ramdisk_name=ramdisk.img\0" \ 138 "ramdisk_addr_r=0x88000000\0" \ 139 "fdtfile=board.dtb\0" \ 140 "fdt_alt_name=juno\0" \ 141 "fdt_addr_r=0x80000000\0" \ 142 143 #ifndef CONFIG_BOOTCOMMAND 144 /* Copy the kernel and FDT to DRAM memory and boot */ 145 #define CONFIG_BOOTCOMMAND "afs load ${kernel_name} ${kernel_addr_r} ;"\ 146 "if test $? -eq 1; then "\ 147 " echo Loading ${kernel_alt_name} instead of "\ 148 "${kernel_name}; "\ 149 " afs load ${kernel_alt_name} ${kernel_addr_r};"\ 150 "fi ; "\ 151 "afs load ${fdtfile} ${fdt_addr_r} ;"\ 152 "if test $? -eq 1; then "\ 153 " echo Loading ${fdt_alt_name} instead of "\ 154 "${fdtfile}; "\ 155 " afs load ${fdt_alt_name} ${fdt_addr_r}; "\ 156 "fi ; "\ 157 "fdt addr ${fdt_addr_r}; fdt resize; " \ 158 "if afs load ${ramdisk_name} ${ramdisk_addr_r} ; "\ 159 "then "\ 160 " setenv ramdisk_param ${ramdisk_addr_r}; "\ 161 " else setenv ramdisk_param -; "\ 162 "fi ; " \ 163 "booti ${kernel_addr_r} ${ramdisk_param} ${fdt_addr_r}" 164 #endif 165 166 167 #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP 168 #define CONFIG_EXTRA_ENV_SETTINGS \ 169 "kernel_name=Image\0" \ 170 "kernel_addr=0x80080000\0" \ 171 "initrd_name=ramdisk.img\0" \ 172 "initrd_addr=0x88000000\0" \ 173 "fdtfile=devtree.dtb\0" \ 174 "fdt_addr=0x83000000\0" \ 175 "boot_name=boot.img\0" \ 176 "boot_addr=0x8007f800\0" 177 178 #ifndef CONFIG_BOOTCOMMAND 179 #define CONFIG_BOOTCOMMAND "if smhload ${boot_name} ${boot_addr}; then " \ 180 " set bootargs; " \ 181 " abootimg addr ${boot_addr}; " \ 182 " abootimg get dtb --index=0 fdt_addr; " \ 183 " bootm ${boot_addr} ${boot_addr} " \ 184 " ${fdt_addr}; " \ 185 "else; " \ 186 " set fdt_high 0xffffffffffffffff; " \ 187 " set initrd_high 0xffffffffffffffff; " \ 188 " smhload ${kernel_name} ${kernel_addr}; " \ 189 " smhload ${fdtfile} ${fdt_addr}; " \ 190 " smhload ${initrd_name} ${initrd_addr} "\ 191 " initrd_end; " \ 192 " fdt addr ${fdt_addr}; fdt resize; " \ 193 " fdt chosen ${initrd_addr} ${initrd_end}; " \ 194 " booti $kernel_addr - $fdt_addr; " \ 195 "fi" 196 #endif 197 #endif 198 199 /* Monitor Command Prompt */ 200 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 201 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 202 203 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO 204 #define CONFIG_SYS_FLASH_BASE 0x08000000 205 /* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */ 206 #define CONFIG_SYS_MAX_FLASH_SECT 259 207 /* Store environment at top of flash in the same location as blank.img */ 208 /* in the Juno firmware. */ 209 #else 210 #define CONFIG_SYS_FLASH_BASE 0x0C000000 211 /* 256 x 256KiB sectors */ 212 #define CONFIG_SYS_MAX_FLASH_SECT 256 213 /* Store environment at top of flash */ 214 #endif 215 216 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT 217 #define CONFIG_SYS_MAX_FLASH_BANKS 1 218 219 #ifdef CONFIG_USB_EHCI_HCD 220 #define CONFIG_USB_OHCI_NEW 221 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 222 #endif 223 224 #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ 225 #define FLASH_MAX_SECTOR_SIZE 0x00040000 226 227 #endif /* __VEXPRESS_AEMV8A_H */ 228