1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Configuation settings for the WB50N CPU Module. 4 */ 5 6 #ifndef __CONFIG_H 7 #define __CONFIG_H 8 9 #include <asm/hardware.h> 10 11 /* ARM asynchronous clock */ 12 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 13 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ 14 15 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 16 #define CONFIG_SETUP_MEMORY_TAGS 17 #define CONFIG_INITRD_TAG 18 19 #ifndef CONFIG_SPL_BUILD 20 #define CONFIG_SKIP_LOWLEVEL_INIT 21 #endif 22 23 /* serial console */ 24 #define CONFIG_USART_BASE ATMEL_BASE_DBGU 25 #define CONFIG_USART_ID ATMEL_ID_DBGU 26 27 /* 28 * BOOTP options 29 */ 30 #define CONFIG_BOOTP_BOOTFILESIZE 31 32 /* SDRAM */ 33 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS 34 #define CONFIG_SYS_SDRAM_SIZE 0x04000000 35 36 #ifdef CONFIG_SPL_BUILD 37 #define CONFIG_SYS_INIT_SP_ADDR 0x310000 38 #else 39 #define CONFIG_SYS_INIT_SP_ADDR \ 40 (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) 41 #endif 42 43 /* NAND flash */ 44 #define CONFIG_SYS_MAX_NAND_DEVICE 1 45 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 46 /* our ALE is AD21 */ 47 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 48 /* our CLE is AD22 */ 49 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 50 #define CONFIG_SYS_NAND_ONFI_DETECTION 51 52 /* Ethernet Hardware */ 53 #define CONFIG_MACB 54 #define CONFIG_RMII 55 #define CONFIG_NET_RETRY_COUNT 20 56 #define CONFIG_MACB_SEARCH_PHY 57 #define CONFIG_RGMII 58 #define CONFIG_ETHADDR C0:EE:40:00:00:00 59 60 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 61 62 #define CONFIG_EXTRA_ENV_SETTINGS \ 63 "autoload=no\0" \ 64 "autostart=no\0" 65 66 /* bootstrap + u-boot + env in nandflash */ 67 #define CONFIG_BOOTCOMMAND \ 68 "nand read 0x22000000 0x000e0000 0x500000; " \ 69 "bootm" 70 71 #define CONFIG_SYS_CBSIZE 1024 72 #define CONFIG_SYS_MAXARGS 16 73 #define CONFIG_SYS_PBSIZE \ 74 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 75 76 /* Size of malloc() pool */ 77 #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) 78 79 /* SPL */ 80 #define CONFIG_SPL_MAX_SIZE 0x10000 81 #define CONFIG_SPL_BSS_START_ADDR 0x20000000 82 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 83 #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 84 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 85 86 #define CONFIG_SYS_MONITOR_LEN (512 << 10) 87 88 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 89 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 90 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 91 #define CONFIG_SYS_NAND_PAGE_COUNT 64 92 #define CONFIG_SYS_NAND_OOBSIZE 64 93 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 94 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 95 96 #endif 97