1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * WORK Microwave work_92105 board configuration file 4 * 5 * (C) Copyright 2014 DENX Software Engineering GmbH 6 * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> 7 */ 8 9 #ifndef __CONFIG_WORK_92105_H__ 10 #define __CONFIG_WORK_92105_H__ 11 12 /* SoC and board defines */ 13 #include <linux/sizes.h> 14 #include <asm/arch/cpu.h> 15 16 /* 17 * Define work_92105 machine type by hand -- done only for compatibility 18 * with original board code 19 */ 20 #define CONFIG_MACH_TYPE 736 21 22 #if !defined(CONFIG_SPL_BUILD) 23 #define CONFIG_SKIP_LOWLEVEL_INIT 24 #endif 25 26 /* 27 * Memory configurations 28 */ 29 #define CONFIG_SYS_MALLOC_LEN SZ_1M 30 #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE 31 #define CONFIG_SYS_SDRAM_SIZE SZ_128M 32 33 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K) 34 35 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \ 36 - GENERATED_GBL_DATA_SIZE) 37 38 /* 39 * Serial Driver 40 */ 41 #define CONFIG_SYS_LPC32XX_UART 5 /* UART5 - NS16550 */ 42 43 /* 44 * Ethernet Driver 45 */ 46 47 #define CONFIG_LPC32XX_ETH 48 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 49 /* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */ 50 51 /* 52 * I2C driver 53 */ 54 55 #define CONFIG_SYS_I2C_LPC32XX 56 #define CONFIG_SYS_I2C 57 #define CONFIG_SYS_I2C_SPEED 350000 58 59 /* 60 * I2C EEPROM 61 */ 62 63 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x56 64 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 65 66 /* 67 * I2C RTC 68 */ 69 70 #define CONFIG_RTC_DS1374 71 72 /* 73 * U-Boot General Configurations 74 */ 75 #define CONFIG_SYS_CBSIZE 1024 76 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 77 78 /* 79 * NAND chip timings for FIXME: which one? 80 */ 81 82 #define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333 83 #define CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000 84 #define CONFIG_LPC32XX_NAND_MLC_NAND_TA 18181818 85 #define CONFIG_LPC32XX_NAND_MLC_RD_HIGH 31250000 86 #define CONFIG_LPC32XX_NAND_MLC_RD_LOW 45454545 87 #define CONFIG_LPC32XX_NAND_MLC_WR_HIGH 40000000 88 #define CONFIG_LPC32XX_NAND_MLC_WR_LOW 83333333 89 90 /* 91 * NAND 92 */ 93 94 /* driver configuration */ 95 #define CONFIG_SYS_NAND_SELF_INIT 96 #define CONFIG_SYS_MAX_NAND_DEVICE 1 97 #define CONFIG_SYS_MAX_NAND_CHIPS 1 98 #define CONFIG_SYS_NAND_BASE MLC_NAND_BASE 99 #define CONFIG_NAND_LPC32XX_MLC 100 101 /* 102 * GPIO 103 */ 104 105 #define CONFIG_LPC32XX_GPIO 106 107 /* 108 * Environment 109 */ 110 111 /* 112 * Boot Linux 113 */ 114 #define CONFIG_CMDLINE_TAG 115 #define CONFIG_SETUP_MEMORY_TAGS 116 #define CONFIG_INITRD_TAG 117 118 #define CONFIG_BOOTFILE "uImage" 119 #define CONFIG_LOADADDR 0x80008000 120 121 /* 122 * SPL 123 */ 124 125 /* SPL will be executed at offset 0 */ 126 /* SPL will use SRAM as stack */ 127 #define CONFIG_SPL_STACK 0x0000FFF8 128 /* Use the framework and generic lib */ 129 /* SPL will use serial */ 130 /* SPL will load U-Boot from NAND offset 0x40000 */ 131 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00040000 132 #define CONFIG_SPL_PAD_TO 0x20000 133 /* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */ 134 #define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */ 135 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 136 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 137 138 /* 139 * Include SoC specific configuration 140 */ 141 #include <asm/arch/config.h> 142 143 #endif /* __CONFIG_WORK_92105_H__*/ 144