1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * (C) Copyright 2018 Xilinx, Inc. (Michal Simek)
4  */
5 
6 #ifndef __CONFIG_ZYNQMP_R5_H
7 #define __CONFIG_ZYNQMP_R5_H
8 
9 #define CONFIG_EXTRA_ENV_SETTINGS
10 
11 /* CPU clock */
12 #define CONFIG_CPU_FREQ_HZ	500000000
13 
14 /* Serial drivers */
15 /* The following table includes the supported baudrates */
16 #define CONFIG_SYS_BAUDRATE_TABLE  \
17 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
18 
19 /* Boot configuration */
20 #define CONFIG_SYS_LOAD_ADDR		0 /* default? */
21 
22 #define CONFIG_SYS_MAXARGS		32 /* max number of command args */
23 
24 #define CONFIG_SYS_MALLOC_LEN		0x1400000
25 
26 #define CONFIG_SYS_INIT_RAM_ADDR	0xFFFF0000
27 #define CONFIG_SYS_INIT_RAM_SIZE	0x1000
28 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
29 					CONFIG_SYS_INIT_RAM_SIZE - \
30 					GENERATED_GBL_DATA_SIZE)
31 
32 /* Extend size of kernel image for uncompression */
33 #define CONFIG_SYS_BOOTM_LEN	(60 * 1024 * 1024)
34 
35 #define CONFIG_SKIP_LOWLEVEL_INIT
36 
37 #endif /* __CONFIG_ZYNQ_ZYNQMP_R5_H */
38