1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2007-2013 Tensilica, Inc. 4 * Copyright (C) 2014 - 2016 Cadence Design Systems Inc. 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #include <asm/arch/core.h> 11 #include <asm/addrspace.h> 12 #include <asm/config.h> 13 14 /* 15 * The 'xtfpga' board describes a set of very similar boards with only minimal 16 * differences. 17 */ 18 19 /*=====================*/ 20 /* Board and Processor */ 21 /*=====================*/ 22 23 #define CONFIG_XTFPGA 24 25 /* FPGA CPU freq after init */ 26 #define CONFIG_SYS_CLK_FREQ (gd->cpu_clk) 27 28 /*===================*/ 29 /* RAM Layout */ 30 /*===================*/ 31 32 #if XCHAL_HAVE_PTP_MMU 33 #define CONFIG_SYS_MEMORY_BASE \ 34 (XCHAL_VECBASE_RESET_VADDR - XCHAL_VECBASE_RESET_PADDR) 35 #define CONFIG_SYS_IO_BASE 0xf0000000 36 #else 37 #define CONFIG_SYS_MEMORY_BASE 0x60000000 38 #define CONFIG_SYS_IO_BASE 0x90000000 39 #define CONFIG_MAX_MEM_MAPPED 0x10000000 40 #endif 41 42 /* Onboard RAM sizes: 43 * 44 * LX60 0x04000000 64 MB 45 * LX110 0x03000000 48 MB 46 * LX200 0x06000000 96 MB 47 * ML605 0x18000000 384 MB 48 * KC705 0x38000000 896 MB 49 * 50 * noMMU configurations can only see first 256MB of onboard memory. 51 */ 52 53 #if XCHAL_HAVE_PTP_MMU || CONFIG_BOARD_SDRAM_SIZE < 0x10000000 54 #define CONFIG_SYS_SDRAM_SIZE CONFIG_BOARD_SDRAM_SIZE 55 #else 56 #define CONFIG_SYS_SDRAM_SIZE 0x10000000 57 #endif 58 59 #define CONFIG_SYS_SDRAM_BASE MEMADDR(0x00000000) 60 61 /* Lx60 can only map 128kb memory (instead of 256kb) when running under OCD */ 62 #ifdef CONFIG_XTFPGA_LX60 63 # define CONFIG_SYS_MONITOR_LEN 0x00020000 /* 128KB */ 64 #else 65 # define CONFIG_SYS_MONITOR_LEN 0x00040000 /* 256KB */ 66 #endif 67 68 #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* heap 256KB */ 69 70 /* Linux boot param area in RAM (used only when booting linux) */ 71 #define CONFIG_SYS_BOOTPARAMS_LEN (64 << 10) 72 73 /* Memory test is destructive so default must not overlap vectors or U-Boot*/ 74 75 /* Load address for stand-alone applications. 76 * MEMADDR cannot be used here, because the definition needs to be 77 * a plain number as it's used as -Ttext argument for ld in standalone 78 * example makefile. 79 * Handle noMMU vs MMUv2 vs MMUv3 distinction here manually. 80 */ 81 #if XCHAL_HAVE_PTP_MMU 82 #if XCHAL_VECBASE_RESET_VADDR == XCHAL_VECBASE_RESET_PADDR 83 #define CONFIG_STANDALONE_LOAD_ADDR 0x00800000 84 #else 85 #define CONFIG_STANDALONE_LOAD_ADDR 0xd0800000 86 #endif 87 #else 88 #define CONFIG_STANDALONE_LOAD_ADDR 0x60800000 89 #endif 90 91 #if defined(CONFIG_MAX_MEM_MAPPED) && \ 92 CONFIG_MAX_MEM_MAPPED < CONFIG_SYS_SDRAM_SIZE 93 #define CONFIG_SYS_MEMORY_SIZE CONFIG_MAX_MEM_MAPPED 94 #else 95 #define CONFIG_SYS_MEMORY_SIZE CONFIG_SYS_SDRAM_SIZE 96 #endif 97 98 #define XTENSA_SYS_TEXT_ADDR \ 99 (MEMADDR(CONFIG_SYS_MEMORY_SIZE) - CONFIG_SYS_MONITOR_LEN) 100 101 /* Used by tftpboot; env var 'loadaddr' */ 102 #define CONFIG_SYS_LOAD_ADDR MEMADDR(0x02000000) 103 104 /*==============================*/ 105 /* U-Boot general configuration */ 106 /*==============================*/ 107 108 #define CONFIG_BOARD_POSTCLK_INIT 109 110 #define CONFIG_BOOTFILE "uImage" 111 /* Console I/O Buffer Size */ 112 #define CONFIG_SYS_CBSIZE 1024 113 /* Boot Argument Buffer Size */ 114 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 115 116 /*==============================*/ 117 /* U-Boot autoboot configuration */ 118 /*==============================*/ 119 120 121 /*=========================================*/ 122 /* FPGA Registers (board info and control) */ 123 /*=========================================*/ 124 125 /* 126 * These assume FPGA bitstreams from Tensilica release RB and up. Earlier 127 * releases may not provide any/all of these registers or at these offsets. 128 * Some of the FPGA registers are broken down into bitfields described by 129 * SHIFT left amount and field WIDTH (bits), and also by a bitMASK. 130 */ 131 132 /* Date of FPGA bitstream build in binary coded decimal (BCD) */ 133 #define CONFIG_SYS_FPGAREG_DATE IOADDR(0x0D020000) 134 #define FPGAREG_MTH_SHIFT 24 /* BCD month 1..12 */ 135 #define FPGAREG_MTH_WIDTH 8 136 #define FPGAREG_MTH_MASK 0xFF000000 137 #define FPGAREG_DAY_SHIFT 16 /* BCD day 1..31 */ 138 #define FPGAREG_DAY_WIDTH 8 139 #define FPGAREG_DAY_MASK 0x00FF0000 140 #define FPGAREG_YEAR_SHIFT 0 /* BCD year 2001..9999*/ 141 #define FPGAREG_YEAR_WIDTH 16 142 #define FPGAREG_YEAR_MASK 0x0000FFFF 143 144 /* FPGA core clock frequency in Hz (also input to UART) */ 145 #define CONFIG_SYS_FPGAREG_FREQ IOADDR(0x0D020004) /* CPU clock frequency*/ 146 147 /* 148 * DIP switch (left=sw1=lsb=bit0, right=sw8=msb=bit7; off=0, on=1): 149 * Bits 0..5 set the lower 6 bits of the default ethernet MAC. 150 * Bit 6 is reserved for future use by Tensilica. 151 * Bit 7 maps the first 128KB of ROM address space at CONFIG_SYS_ROM_BASE to 152 * the base of flash * (when on/1) or to the base of RAM (when off/0). 153 */ 154 #define CONFIG_SYS_FPGAREG_DIPSW IOADDR(0x0D02000C) 155 #define FPGAREG_MAC_SHIFT 0 /* Ethernet MAC bits 0..5 */ 156 #define FPGAREG_MAC_WIDTH 6 157 #define FPGAREG_MAC_MASK 0x3f 158 #define FPGAREG_BOOT_SHIFT 7 /* Boot ROM addr mapping */ 159 #define FPGAREG_BOOT_WIDTH 1 160 #define FPGAREG_BOOT_MASK 0x80 161 #define FPGAREG_BOOT_RAM 0 162 #define FPGAREG_BOOT_FLASH (1<<FPGAREG_BOOT_SHIFT) 163 164 /* Force hard reset of board by writing a code to this register */ 165 #define CONFIG_SYS_FPGAREG_RESET IOADDR(0x0D020010) /* Reset board .. */ 166 #define CONFIG_SYS_FPGAREG_RESET_CODE 0x0000DEAD /* by writing this code */ 167 168 /*====================*/ 169 /* Serial Driver Info */ 170 /*====================*/ 171 172 #define CONFIG_SYS_NS16550_SERIAL 173 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 174 #define CONFIG_SYS_NS16550_COM1 IOADDR(0x0D050020) /* Base address */ 175 176 /* Input clk to NS16550 (in Hz; the SYS_CLK_FREQ is in kHz) */ 177 #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_CLK_FREQ 178 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 179 180 /*======================*/ 181 /* Ethernet Driver Info */ 182 /*======================*/ 183 184 #define CONFIG_ETHBASE 00:50:C2:13:6f:00 185 #define CONFIG_SYS_ETHOC_BASE IOADDR(0x0d030000) 186 #define CONFIG_SYS_ETHOC_BUFFER_ADDR IOADDR(0x0D800000) 187 188 /*=====================*/ 189 /* Flash & Environment */ 190 /*=====================*/ 191 192 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 193 #define CONFIG_SYS_MAX_FLASH_BANKS 1 194 #ifdef CONFIG_XTFPGA_LX60 195 # define CONFIG_SYS_FLASH_SIZE 0x0040000 /* 4MB */ 196 # define CONFIG_SYS_FLASH_SECT_SZ 0x10000 /* block size 64KB */ 197 # define CONFIG_SYS_FLASH_PARMSECT_SZ 0x2000 /* param size 8KB */ 198 # define CONFIG_SYS_FLASH_BASE IOADDR(0x08000000) 199 # define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 200 #elif defined(CONFIG_XTFPGA_KC705) 201 # define CONFIG_SYS_FLASH_SIZE 0x8000000 /* 128MB */ 202 # define CONFIG_SYS_FLASH_SECT_SZ 0x20000 /* block size 128KB */ 203 # define CONFIG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */ 204 # define CONFIG_SYS_FLASH_BASE IOADDR(0x00000000) 205 # define CONFIG_SYS_MONITOR_BASE IOADDR(0x06000000) 206 #else 207 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* 16MB */ 208 # define CONFIG_SYS_FLASH_SECT_SZ 0x20000 /* block size 128KB */ 209 # define CONFIG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */ 210 # define CONFIG_SYS_FLASH_BASE IOADDR(0x08000000) 211 # define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 212 #endif 213 #define CONFIG_SYS_MAX_FLASH_SECT \ 214 (CONFIG_SYS_FLASH_SECT_SZ/CONFIG_SYS_FLASH_PARMSECT_SZ + \ 215 CONFIG_SYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ - 1) 216 217 /* 218 * Put environment in top block (64kB) 219 * Another option would be to put env. in 2nd param block offs 8KB, size 8KB 220 */ 221 222 /* print 'E' for empty sector on flinfo */ 223 #define CONFIG_SYS_FLASH_EMPTY_INFO 224 225 #endif /* __CONFIG_H */ 226