1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Defines APIs and structures that allow software to interact with a 4 * TPM2 device 5 * 6 * Copyright (c) 2020 Linaro 7 * Copyright (c) 2018 Bootlin 8 * 9 * https://trustedcomputinggroup.org/resource/tss-overview-common-structures-specification/ 10 * 11 * Author: Miquel Raynal <miquel.raynal@bootlin.com> 12 */ 13 14 #ifndef __TPM_V2_H 15 #define __TPM_V2_H 16 17 #include <tpm-common.h> 18 19 struct udevice; 20 21 #define TPM2_DIGEST_LEN 32 22 23 #define TPM2_SHA1_DIGEST_SIZE 20 24 #define TPM2_SHA256_DIGEST_SIZE 32 25 #define TPM2_SHA384_DIGEST_SIZE 48 26 #define TPM2_SHA512_DIGEST_SIZE 64 27 #define TPM2_SM3_256_DIGEST_SIZE 32 28 29 #define TPM2_MAX_PCRS 32 30 #define TPM2_PCR_SELECT_MAX ((TPM2_MAX_PCRS + 7) / 8) 31 #define TPM2_MAX_CAP_BUFFER 1024 32 #define TPM2_MAX_TPM_PROPERTIES ((TPM2_MAX_CAP_BUFFER - sizeof(u32) /* TPM2_CAP */ - \ 33 sizeof(u32)) / sizeof(struct tpms_tagged_property)) 34 35 /* 36 * We deviate from this draft of the specification by increasing the value of 37 * TPM2_NUM_PCR_BANKS from 3 to 16 to ensure compatibility with TPM2 38 * implementations that have enabled a larger than typical number of PCR 39 * banks. This larger value for TPM2_NUM_PCR_BANKS is expected to be included 40 * in a future revision of the specification. 41 */ 42 #define TPM2_NUM_PCR_BANKS 16 43 44 /* Definition of (UINT32) TPM2_CAP Constants */ 45 #define TPM2_CAP_PCRS 0x00000005U 46 #define TPM2_CAP_TPM_PROPERTIES 0x00000006U 47 48 /* Definition of (UINT32) TPM2_PT Constants */ 49 #define TPM2_PT_GROUP (u32)(0x00000100) 50 #define TPM2_PT_FIXED (u32)(TPM2_PT_GROUP * 1) 51 #define TPM2_PT_MANUFACTURER (u32)(TPM2_PT_FIXED + 5) 52 #define TPM2_PT_PCR_COUNT (u32)(TPM2_PT_FIXED + 18) 53 #define TPM2_PT_MAX_COMMAND_SIZE (u32)(TPM2_PT_FIXED + 30) 54 #define TPM2_PT_MAX_RESPONSE_SIZE (u32)(TPM2_PT_FIXED + 31) 55 56 /* event types */ 57 #define EV_POST_CODE ((u32)0x00000001) 58 #define EV_NO_ACTION ((u32)0x00000003) 59 #define EV_SEPARATOR ((u32)0x00000004) 60 #define EV_S_CRTM_CONTENTS ((u32)0x00000007) 61 #define EV_S_CRTM_VERSION ((u32)0x00000008) 62 #define EV_CPU_MICROCODE ((u32)0x00000009) 63 #define EV_TABLE_OF_DEVICES ((u32)0x0000000B) 64 65 /* TPMS_TAGGED_PROPERTY Structure */ 66 struct tpms_tagged_property { 67 u32 property; 68 u32 value; 69 } __packed; 70 71 /* TPMS_PCR_SELECTION Structure */ 72 struct tpms_pcr_selection { 73 u16 hash; 74 u8 size_of_select; 75 u8 pcr_select[TPM2_PCR_SELECT_MAX]; 76 } __packed; 77 78 /* TPML_PCR_SELECTION Structure */ 79 struct tpml_pcr_selection { 80 u32 count; 81 struct tpms_pcr_selection selection[TPM2_NUM_PCR_BANKS]; 82 } __packed; 83 84 /* TPML_TAGGED_TPM_PROPERTY Structure */ 85 struct tpml_tagged_tpm_property { 86 u32 count; 87 struct tpms_tagged_property tpm_property[TPM2_MAX_TPM_PROPERTIES]; 88 } __packed; 89 90 /* TPMU_CAPABILITIES Union */ 91 union tpmu_capabilities { 92 /* 93 * Non exhaustive. Only added the structs needed for our 94 * current code 95 */ 96 struct tpml_pcr_selection assigned_pcr; 97 struct tpml_tagged_tpm_property tpm_properties; 98 } __packed; 99 100 /* TPMS_CAPABILITY_DATA Structure */ 101 struct tpms_capability_data { 102 u32 capability; 103 union tpmu_capabilities data; 104 } __packed; 105 106 /** 107 * SHA1 Event Log Entry Format 108 * 109 * @pcr_index: PCRIndex event extended to 110 * @event_type: Type of event (see EFI specs) 111 * @digest: Value extended into PCR index 112 * @event_size: Size of event 113 * @event: Event data 114 */ 115 struct tcg_pcr_event { 116 u32 pcr_index; 117 u32 event_type; 118 u8 digest[TPM2_SHA1_DIGEST_SIZE]; 119 u32 event_size; 120 u8 event[]; 121 } __packed; 122 123 /** 124 * Definition of TPMU_HA Union 125 */ 126 union tmpu_ha { 127 u8 sha1[TPM2_SHA1_DIGEST_SIZE]; 128 u8 sha256[TPM2_SHA256_DIGEST_SIZE]; 129 u8 sm3_256[TPM2_SM3_256_DIGEST_SIZE]; 130 u8 sha384[TPM2_SHA384_DIGEST_SIZE]; 131 u8 sha512[TPM2_SHA512_DIGEST_SIZE]; 132 } __packed; 133 134 /** 135 * Definition of TPMT_HA Structure 136 * 137 * @hash_alg: Hash algorithm defined in enum tpm2_algorithms 138 * @digest: Digest value for a given algorithm 139 */ 140 struct tpmt_ha { 141 u16 hash_alg; 142 union tmpu_ha digest; 143 } __packed; 144 145 /** 146 * Definition of TPML_DIGEST_VALUES Structure 147 * 148 * @count: Number of algorithms supported by hardware 149 * @digests: struct for algorithm id and hash value 150 */ 151 struct tpml_digest_values { 152 u32 count; 153 struct tpmt_ha digests[TPM2_NUM_PCR_BANKS]; 154 } __packed; 155 156 /** 157 * Crypto Agile Log Entry Format 158 * 159 * @pcr_index: PCRIndex event extended to 160 * @event_type: Type of event 161 * @digests: List of digestsextended to PCR index 162 * @event_size: Size of the event data 163 * @event: Event data 164 */ 165 struct tcg_pcr_event2 { 166 u32 pcr_index; 167 u32 event_type; 168 struct tpml_digest_values digests; 169 u32 event_size; 170 u8 event[]; 171 } __packed; 172 173 /** 174 * TPM2 Structure Tags for command/response buffers. 175 * 176 * @TPM2_ST_NO_SESSIONS: the command does not need an authentication. 177 * @TPM2_ST_SESSIONS: the command needs an authentication. 178 */ 179 enum tpm2_structures { 180 TPM2_ST_NO_SESSIONS = 0x8001, 181 TPM2_ST_SESSIONS = 0x8002, 182 }; 183 184 /** 185 * TPM2 type of boolean. 186 */ 187 enum tpm2_yes_no { 188 TPMI_YES = 1, 189 TPMI_NO = 0, 190 }; 191 192 /** 193 * TPM2 startup values. 194 * 195 * @TPM2_SU_CLEAR: reset the internal state. 196 * @TPM2_SU_STATE: restore saved state (if any). 197 */ 198 enum tpm2_startup_types { 199 TPM2_SU_CLEAR = 0x0000, 200 TPM2_SU_STATE = 0x0001, 201 }; 202 203 /** 204 * TPM2 permanent handles. 205 * 206 * @TPM2_RH_OWNER: refers to the 'owner' hierarchy. 207 * @TPM2_RS_PW: indicates a password. 208 * @TPM2_RH_LOCKOUT: refers to the 'lockout' hierarchy. 209 * @TPM2_RH_ENDORSEMENT: refers to the 'endorsement' hierarchy. 210 * @TPM2_RH_PLATFORM: refers to the 'platform' hierarchy. 211 */ 212 enum tpm2_handles { 213 TPM2_RH_OWNER = 0x40000001, 214 TPM2_RS_PW = 0x40000009, 215 TPM2_RH_LOCKOUT = 0x4000000A, 216 TPM2_RH_ENDORSEMENT = 0x4000000B, 217 TPM2_RH_PLATFORM = 0x4000000C, 218 }; 219 220 /** 221 * TPM2 command codes used at the beginning of a buffer, gives the command. 222 * 223 * @TPM2_CC_STARTUP: TPM2_Startup(). 224 * @TPM2_CC_SELF_TEST: TPM2_SelfTest(). 225 * @TPM2_CC_CLEAR: TPM2_Clear(). 226 * @TPM2_CC_CLEARCONTROL: TPM2_ClearControl(). 227 * @TPM2_CC_HIERCHANGEAUTH: TPM2_HierarchyChangeAuth(). 228 * @TPM2_CC_PCR_SETAUTHPOL: TPM2_PCR_SetAuthPolicy(). 229 * @TPM2_CC_DAM_RESET: TPM2_DictionaryAttackLockReset(). 230 * @TPM2_CC_DAM_PARAMETERS: TPM2_DictionaryAttackParameters(). 231 * @TPM2_CC_GET_CAPABILITY: TPM2_GetCapibility(). 232 * @TPM2_CC_GET_RANDOM: TPM2_GetRandom(). 233 * @TPM2_CC_PCR_READ: TPM2_PCR_Read(). 234 * @TPM2_CC_PCR_EXTEND: TPM2_PCR_Extend(). 235 * @TPM2_CC_PCR_SETAUTHVAL: TPM2_PCR_SetAuthValue(). 236 */ 237 enum tpm2_command_codes { 238 TPM2_CC_STARTUP = 0x0144, 239 TPM2_CC_SELF_TEST = 0x0143, 240 TPM2_CC_CLEAR = 0x0126, 241 TPM2_CC_CLEARCONTROL = 0x0127, 242 TPM2_CC_HIERCHANGEAUTH = 0x0129, 243 TPM2_CC_PCR_SETAUTHPOL = 0x012C, 244 TPM2_CC_DAM_RESET = 0x0139, 245 TPM2_CC_DAM_PARAMETERS = 0x013A, 246 TPM2_CC_NV_READ = 0x014E, 247 TPM2_CC_GET_CAPABILITY = 0x017A, 248 TPM2_CC_GET_RANDOM = 0x017B, 249 TPM2_CC_PCR_READ = 0x017E, 250 TPM2_CC_PCR_EXTEND = 0x0182, 251 TPM2_CC_PCR_SETAUTHVAL = 0x0183, 252 }; 253 254 /** 255 * TPM2 return codes. 256 */ 257 enum tpm2_return_codes { 258 TPM2_RC_SUCCESS = 0x0000, 259 TPM2_RC_BAD_TAG = 0x001E, 260 TPM2_RC_FMT1 = 0x0080, 261 TPM2_RC_HASH = TPM2_RC_FMT1 + 0x0003, 262 TPM2_RC_VALUE = TPM2_RC_FMT1 + 0x0004, 263 TPM2_RC_SIZE = TPM2_RC_FMT1 + 0x0015, 264 TPM2_RC_BAD_AUTH = TPM2_RC_FMT1 + 0x0022, 265 TPM2_RC_HANDLE = TPM2_RC_FMT1 + 0x000B, 266 TPM2_RC_VER1 = 0x0100, 267 TPM2_RC_INITIALIZE = TPM2_RC_VER1 + 0x0000, 268 TPM2_RC_FAILURE = TPM2_RC_VER1 + 0x0001, 269 TPM2_RC_DISABLED = TPM2_RC_VER1 + 0x0020, 270 TPM2_RC_AUTH_MISSING = TPM2_RC_VER1 + 0x0025, 271 TPM2_RC_COMMAND_CODE = TPM2_RC_VER1 + 0x0043, 272 TPM2_RC_AUTHSIZE = TPM2_RC_VER1 + 0x0044, 273 TPM2_RC_AUTH_CONTEXT = TPM2_RC_VER1 + 0x0045, 274 TPM2_RC_NEEDS_TEST = TPM2_RC_VER1 + 0x0053, 275 TPM2_RC_WARN = 0x0900, 276 TPM2_RC_TESTING = TPM2_RC_WARN + 0x000A, 277 TPM2_RC_REFERENCE_H0 = TPM2_RC_WARN + 0x0010, 278 TPM2_RC_LOCKOUT = TPM2_RC_WARN + 0x0021, 279 }; 280 281 /** 282 * TPM2 algorithms. 283 */ 284 enum tpm2_algorithms { 285 TPM2_ALG_SHA1 = 0x04, 286 TPM2_ALG_XOR = 0x0A, 287 TPM2_ALG_SHA256 = 0x0B, 288 TPM2_ALG_SHA384 = 0x0C, 289 TPM2_ALG_SHA512 = 0x0D, 290 TPM2_ALG_NULL = 0x10, 291 TPM2_ALG_SM3_256 = 0x12, 292 }; 293 294 /* NV index attributes */ 295 enum tpm_index_attrs { 296 TPMA_NV_PPWRITE = 1UL << 0, 297 TPMA_NV_OWNERWRITE = 1UL << 1, 298 TPMA_NV_AUTHWRITE = 1UL << 2, 299 TPMA_NV_POLICYWRITE = 1UL << 3, 300 TPMA_NV_COUNTER = 1UL << 4, 301 TPMA_NV_BITS = 1UL << 5, 302 TPMA_NV_EXTEND = 1UL << 6, 303 TPMA_NV_POLICY_DELETE = 1UL << 10, 304 TPMA_NV_WRITELOCKED = 1UL << 11, 305 TPMA_NV_WRITEALL = 1UL << 12, 306 TPMA_NV_WRITEDEFINE = 1UL << 13, 307 TPMA_NV_WRITE_STCLEAR = 1UL << 14, 308 TPMA_NV_GLOBALLOCK = 1UL << 15, 309 TPMA_NV_PPREAD = 1UL << 16, 310 TPMA_NV_OWNERREAD = 1UL << 17, 311 TPMA_NV_AUTHREAD = 1UL << 18, 312 TPMA_NV_POLICYREAD = 1UL << 19, 313 TPMA_NV_NO_DA = 1UL << 25, 314 TPMA_NV_ORDERLY = 1UL << 26, 315 TPMA_NV_CLEAR_STCLEAR = 1UL << 27, 316 TPMA_NV_READLOCKED = 1UL << 28, 317 TPMA_NV_WRITTEN = 1UL << 29, 318 TPMA_NV_PLATFORMCREATE = 1UL << 30, 319 TPMA_NV_READ_STCLEAR = 1UL << 31, 320 321 TPMA_NV_MASK_READ = TPMA_NV_PPREAD | TPMA_NV_OWNERREAD | 322 TPMA_NV_AUTHREAD | TPMA_NV_POLICYREAD, 323 TPMA_NV_MASK_WRITE = TPMA_NV_PPWRITE | TPMA_NV_OWNERWRITE | 324 TPMA_NV_AUTHWRITE | TPMA_NV_POLICYWRITE, 325 }; 326 327 enum { 328 TPM_ACCESS_VALID = 1 << 7, 329 TPM_ACCESS_ACTIVE_LOCALITY = 1 << 5, 330 TPM_ACCESS_REQUEST_PENDING = 1 << 2, 331 TPM_ACCESS_REQUEST_USE = 1 << 1, 332 TPM_ACCESS_ESTABLISHMENT = 1 << 0, 333 }; 334 335 enum { 336 TPM_STS_FAMILY_SHIFT = 26, 337 TPM_STS_FAMILY_MASK = 0x3 << TPM_STS_FAMILY_SHIFT, 338 TPM_STS_FAMILY_TPM2 = 1 << TPM_STS_FAMILY_SHIFT, 339 TPM_STS_RESE_TESTABLISMENT_BIT = 1 << 25, 340 TPM_STS_COMMAND_CANCEL = 1 << 24, 341 TPM_STS_BURST_COUNT_SHIFT = 8, 342 TPM_STS_BURST_COUNT_MASK = 0xffff << TPM_STS_BURST_COUNT_SHIFT, 343 TPM_STS_VALID = 1 << 7, 344 TPM_STS_COMMAND_READY = 1 << 6, 345 TPM_STS_GO = 1 << 5, 346 TPM_STS_DATA_AVAIL = 1 << 4, 347 TPM_STS_DATA_EXPECT = 1 << 3, 348 TPM_STS_SELF_TEST_DONE = 1 << 2, 349 TPM_STS_RESPONSE_RETRY = 1 << 1, 350 }; 351 352 enum { 353 TPM_CMD_COUNT_OFFSET = 2, 354 TPM_CMD_ORDINAL_OFFSET = 6, 355 TPM_MAX_BUF_SIZE = 1260, 356 }; 357 358 /** 359 * Issue a TPM2_Startup command. 360 * 361 * @dev TPM device 362 * @mode TPM startup mode 363 * 364 * @return code of the operation 365 */ 366 u32 tpm2_startup(struct udevice *dev, enum tpm2_startup_types mode); 367 368 /** 369 * Issue a TPM2_SelfTest command. 370 * 371 * @dev TPM device 372 * @full_test Asking to perform all tests or only the untested ones 373 * 374 * @return code of the operation 375 */ 376 u32 tpm2_self_test(struct udevice *dev, enum tpm2_yes_no full_test); 377 378 /** 379 * Issue a TPM2_Clear command. 380 * 381 * @dev TPM device 382 * @handle Handle 383 * @pw Password 384 * @pw_sz Length of the password 385 * 386 * @return code of the operation 387 */ 388 u32 tpm2_clear(struct udevice *dev, u32 handle, const char *pw, 389 const ssize_t pw_sz); 390 391 /** 392 * Issue a TPM2_PCR_Extend command. 393 * 394 * @dev TPM device 395 * @index Index of the PCR 396 * @algorithm Algorithm used, defined in 'enum tpm2_algorithms' 397 * @digest Value representing the event to be recorded 398 * @digest_len len of the hash 399 * 400 * @return code of the operation 401 */ 402 u32 tpm2_pcr_extend(struct udevice *dev, u32 index, u32 algorithm, 403 const u8 *digest, u32 digest_len); 404 405 /** 406 * Issue a TPM2_PCR_Read command. 407 * 408 * @dev TPM device 409 * @idx Index of the PCR 410 * @idx_min_sz Minimum size in bytes of the pcrSelect array 411 * @data Output buffer for contents of the named PCR 412 * @updates Optional out parameter: number of updates for this PCR 413 * 414 * @return code of the operation 415 */ 416 u32 tpm2_pcr_read(struct udevice *dev, u32 idx, unsigned int idx_min_sz, 417 void *data, unsigned int *updates); 418 419 /** 420 * Issue a TPM2_GetCapability command. This implementation is limited 421 * to query property index that is 4-byte wide. 422 * 423 * @dev TPM device 424 * @capability Partition of capabilities 425 * @property Further definition of capability, limited to be 4 bytes wide 426 * @buf Output buffer for capability information 427 * @prop_count Size of output buffer 428 * 429 * @return code of the operation 430 */ 431 u32 tpm2_get_capability(struct udevice *dev, u32 capability, u32 property, 432 void *buf, size_t prop_count); 433 434 /** 435 * Issue a TPM2_DictionaryAttackLockReset command. 436 * 437 * @dev TPM device 438 * @pw Password 439 * @pw_sz Length of the password 440 * 441 * @return code of the operation 442 */ 443 u32 tpm2_dam_reset(struct udevice *dev, const char *pw, const ssize_t pw_sz); 444 445 /** 446 * Issue a TPM2_DictionaryAttackParameters command. 447 * 448 * @dev TPM device 449 * @pw Password 450 * @pw_sz Length of the password 451 * @max_tries Count of authorizations before lockout 452 * @recovery_time Time before decrementation of the failure count 453 * @lockout_recovery Time to wait after a lockout 454 * 455 * @return code of the operation 456 */ 457 u32 tpm2_dam_parameters(struct udevice *dev, const char *pw, 458 const ssize_t pw_sz, unsigned int max_tries, 459 unsigned int recovery_time, 460 unsigned int lockout_recovery); 461 462 /** 463 * Issue a TPM2_HierarchyChangeAuth command. 464 * 465 * @dev TPM device 466 * @handle Handle 467 * @newpw New password 468 * @newpw_sz Length of the new password 469 * @oldpw Old password 470 * @oldpw_sz Length of the old password 471 * 472 * @return code of the operation 473 */ 474 int tpm2_change_auth(struct udevice *dev, u32 handle, const char *newpw, 475 const ssize_t newpw_sz, const char *oldpw, 476 const ssize_t oldpw_sz); 477 478 /** 479 * Issue a TPM_PCR_SetAuthPolicy command. 480 * 481 * @dev TPM device 482 * @pw Platform password 483 * @pw_sz Length of the password 484 * @index Index of the PCR 485 * @digest New key to access the PCR 486 * 487 * @return code of the operation 488 */ 489 u32 tpm2_pcr_setauthpolicy(struct udevice *dev, const char *pw, 490 const ssize_t pw_sz, u32 index, const char *key); 491 492 /** 493 * Issue a TPM_PCR_SetAuthValue command. 494 * 495 * @dev TPM device 496 * @pw Platform password 497 * @pw_sz Length of the password 498 * @index Index of the PCR 499 * @digest New key to access the PCR 500 * @key_sz Length of the new key 501 * 502 * @return code of the operation 503 */ 504 u32 tpm2_pcr_setauthvalue(struct udevice *dev, const char *pw, 505 const ssize_t pw_sz, u32 index, const char *key, 506 const ssize_t key_sz); 507 508 /** 509 * Issue a TPM2_GetRandom command. 510 * 511 * @dev TPM device 512 * @param data output buffer for the random bytes 513 * @param count size of output buffer 514 * 515 * @return return code of the operation 516 */ 517 u32 tpm2_get_random(struct udevice *dev, void *data, u32 count); 518 519 #endif /* __TPM_V2_H */ 520