1 /******************************************************************************
2 * ns16550.c
3 *
4 * Driver for 16550-series UARTs. This driver is to be kept within Xen as
5 * it permits debugging of seriously-toasted machines (e.g., in situations
6 * where a device driver within a guest OS would be inaccessible).
7 *
8 * Copyright (c) 2003-2005, K A Fraser
9 */
10
11 #include <xen/console.h>
12 #include <xen/init.h>
13 #include <xen/irq.h>
14 #include <xen/param.h>
15 #include <xen/sched.h>
16 #include <xen/timer.h>
17 #include <xen/serial.h>
18 #include <xen/iocap.h>
19 #ifdef CONFIG_HAS_PCI
20 #include <xen/pci.h>
21 #include <xen/pci_regs.h>
22 #include <xen/pci_ids.h>
23 #endif
24 #include <xen/8250-uart.h>
25 #include <xen/vmap.h>
26 #include <asm/io.h>
27 #ifdef CONFIG_HAS_DEVICE_TREE
28 #include <asm/device.h>
29 #endif
30 #ifdef CONFIG_X86
31 #include <asm/fixmap.h>
32 #endif
33
34 /*
35 * Configure serial port with a string:
36 * <baud>[/<base_baud>][,DPS[,<io-base>[,<irq>[,<port-bdf>[,<bridge-bdf>]]]]].
37 * The tail of the string can be omitted if platform defaults are sufficient.
38 * If the baud rate is pre-configured, perhaps by a bootloader, then 'auto'
39 * can be specified in place of a numeric baud rate. Polled mode is specified
40 * by requesting irq 0.
41 */
42 static char __initdata opt_com1[128] = "";
43 static char __initdata opt_com2[128] = "";
44 string_param("com1", opt_com1);
45 string_param("com2", opt_com2);
46
47 enum serial_param_type {
48 baud,
49 clock_hz,
50 data_bits,
51 io_base,
52 irq,
53 parity,
54 reg_shift,
55 reg_width,
56 stop_bits,
57 #ifdef CONFIG_HAS_PCI
58 bridge_bdf,
59 device,
60 port_bdf,
61 #endif
62 /* List all parameters before this line. */
63 num_serial_params
64 };
65
66 static struct ns16550 {
67 int baud, clock_hz, data_bits, parity, stop_bits, fifo_size, irq;
68 u64 io_base; /* I/O port or memory-mapped I/O address. */
69 u64 io_size;
70 int reg_shift; /* Bits to shift register offset by */
71 int reg_width; /* Size of access to use, the registers
72 * themselves are still bytes */
73 char __iomem *remapped_io_base; /* Remapped virtual address of MMIO. */
74 /* UART with IRQ line: interrupt-driven I/O. */
75 struct irqaction irqaction;
76 u8 lsr_mask;
77 #ifdef CONFIG_ARM
78 struct vuart_info vuart;
79 #endif
80 /* UART with no IRQ line: periodically-polled I/O. */
81 struct timer timer;
82 struct timer resume_timer;
83 unsigned int timeout_ms;
84 bool_t intr_works;
85 bool_t dw_usr_bsy;
86 #ifdef CONFIG_HAS_PCI
87 /* PCI card parameters. */
88 bool_t pb_bdf_enable; /* if =1, pb-bdf effective, port behind bridge */
89 bool_t ps_bdf_enable; /* if =1, ps_bdf effective, port on pci card */
90 unsigned int pb_bdf[3]; /* pci bridge BDF */
91 unsigned int ps_bdf[3]; /* pci serial port BDF */
92 u32 bar;
93 u32 bar64;
94 u16 cr;
95 u8 bar_idx;
96 bool msi;
97 const struct ns16550_config_param *param; /* Points into .init.*! */
98 #endif
99 } ns16550_com[2] = { { 0 } };
100
101 struct serial_param_var {
102 char name[12];
103 enum serial_param_type type;
104 };
105
106 /*
107 * Enum struct keeping a table of all accepted parameter names for parsing
108 * com_console_options for serial port com1 and com2.
109 */
110 static const struct serial_param_var __initconst sp_vars[] = {
111 {"baud", baud},
112 {"clock-hz", clock_hz},
113 {"data-bits", data_bits},
114 {"io-base", io_base},
115 {"irq", irq},
116 {"parity", parity},
117 {"reg-shift", reg_shift},
118 {"reg-width", reg_width},
119 {"stop-bits", stop_bits},
120 #ifdef CONFIG_HAS_PCI
121 {"bridge", bridge_bdf},
122 {"dev", device},
123 {"port", port_bdf},
124 #endif
125 };
126
127 #ifdef CONFIG_HAS_PCI
128 struct ns16550_config {
129 u16 vendor_id;
130 u16 dev_id;
131 enum {
132 param_default, /* Must not be referenced by any table entry. */
133 param_trumanage,
134 param_oxford,
135 param_oxford_2port,
136 param_pericom_1port,
137 param_pericom_2port,
138 param_pericom_4port,
139 param_pericom_8port,
140 } param;
141 };
142
143 /* Defining uart config options for MMIO devices */
144 struct ns16550_config_param {
145 unsigned int reg_shift;
146 unsigned int reg_width;
147 unsigned int fifo_size;
148 u8 lsr_mask;
149 bool_t mmio;
150 bool_t bar0;
151 unsigned int max_ports;
152 unsigned int base_baud;
153 unsigned int uart_offset;
154 unsigned int first_offset;
155 };
156
157 /*
158 * Create lookup tables for specific devices. It is assumed that if
159 * the device found is MMIO, then you have indexed it here. Else, the
160 * driver does nothing for MMIO based devices.
161 */
162 static const struct ns16550_config_param __initconst uart_param[] = {
163 [param_default] = {
164 .reg_width = 1,
165 .lsr_mask = UART_LSR_THRE,
166 .max_ports = 1,
167 },
168 [param_trumanage] = {
169 .reg_shift = 2,
170 .reg_width = 1,
171 .fifo_size = 16,
172 .lsr_mask = (UART_LSR_THRE | UART_LSR_TEMT),
173 .mmio = 1,
174 .max_ports = 1,
175 },
176 [param_oxford] = {
177 .base_baud = 4000000,
178 .uart_offset = 0x200,
179 .first_offset = 0x1000,
180 .reg_width = 1,
181 .fifo_size = 16,
182 .lsr_mask = UART_LSR_THRE,
183 .mmio = 1,
184 .max_ports = 1, /* It can do more, but we would need more custom code.*/
185 },
186 [param_oxford_2port] = {
187 .base_baud = 4000000,
188 .uart_offset = 0x200,
189 .first_offset = 0x1000,
190 .reg_width = 1,
191 .fifo_size = 16,
192 .lsr_mask = UART_LSR_THRE,
193 .mmio = 1,
194 .max_ports = 2,
195 },
196 [param_pericom_1port] = {
197 .base_baud = 921600,
198 .uart_offset = 8,
199 .reg_width = 1,
200 .fifo_size = 16,
201 .lsr_mask = UART_LSR_THRE,
202 .bar0 = 1,
203 .max_ports = 1,
204 },
205 [param_pericom_2port] = {
206 .base_baud = 921600,
207 .uart_offset = 8,
208 .reg_width = 1,
209 .fifo_size = 16,
210 .lsr_mask = UART_LSR_THRE,
211 .bar0 = 1,
212 .max_ports = 2,
213 },
214 /*
215 * Of the two following ones, we can't really use all of their ports,
216 * unless ns16550_com[] would get grown.
217 */
218 [param_pericom_4port] = {
219 .base_baud = 921600,
220 .uart_offset = 8,
221 .reg_width = 1,
222 .fifo_size = 16,
223 .lsr_mask = UART_LSR_THRE,
224 .bar0 = 1,
225 .max_ports = 4,
226 },
227 [param_pericom_8port] = {
228 .base_baud = 921600,
229 .uart_offset = 8,
230 .reg_width = 1,
231 .fifo_size = 16,
232 .lsr_mask = UART_LSR_THRE,
233 .bar0 = 1,
234 .max_ports = 8,
235 }
236 };
237 static const struct ns16550_config __initconst uart_config[] =
238 {
239 /* Broadcom TruManage device */
240 {
241 .vendor_id = PCI_VENDOR_ID_BROADCOM,
242 .dev_id = 0x160a,
243 .param = param_trumanage,
244 },
245 /* OXPCIe952 1 Native UART */
246 {
247 .vendor_id = PCI_VENDOR_ID_OXSEMI,
248 .dev_id = 0xc11b,
249 .param = param_oxford,
250 },
251 /* OXPCIe952 1 Native UART */
252 {
253 .vendor_id = PCI_VENDOR_ID_OXSEMI,
254 .dev_id = 0xc11f,
255 .param = param_oxford,
256 },
257 /* OXPCIe952 1 Native UART */
258 {
259 .vendor_id = PCI_VENDOR_ID_OXSEMI,
260 .dev_id = 0xc138,
261 .param = param_oxford,
262 },
263 /* OXPCIe952 2 Native UART */
264 {
265 .vendor_id = PCI_VENDOR_ID_OXSEMI,
266 .dev_id = 0xc158,
267 .param = param_oxford_2port,
268 },
269 /* OXPCIe952 1 Native UART */
270 {
271 .vendor_id = PCI_VENDOR_ID_OXSEMI,
272 .dev_id = 0xc13d,
273 .param = param_oxford,
274 },
275 /* OXPCIe952 2 Native UART */
276 {
277 .vendor_id = PCI_VENDOR_ID_OXSEMI,
278 .dev_id = 0xc15d,
279 .param = param_oxford_2port,
280 },
281 /* OXPCIe952 1 Native UART */
282 {
283 .vendor_id = PCI_VENDOR_ID_OXSEMI,
284 .dev_id = 0xc40b,
285 .param = param_oxford,
286 },
287 /* OXPCIe200 1 Native UART */
288 {
289 .vendor_id = PCI_VENDOR_ID_OXSEMI,
290 .dev_id = 0xc40f,
291 .param = param_oxford,
292 },
293 /* OXPCIe200 1 Native UART */
294 {
295 .vendor_id = PCI_VENDOR_ID_OXSEMI,
296 .dev_id = 0xc41b,
297 .param = param_oxford,
298 },
299 /* OXPCIe200 1 Native UART */
300 {
301 .vendor_id = PCI_VENDOR_ID_OXSEMI,
302 .dev_id = 0xc41f,
303 .param = param_oxford,
304 },
305 /* OXPCIe200 1 Native UART */
306 {
307 .vendor_id = PCI_VENDOR_ID_OXSEMI,
308 .dev_id = 0xc42b,
309 .param = param_oxford,
310 },
311 /* OXPCIe200 1 Native UART */
312 {
313 .vendor_id = PCI_VENDOR_ID_OXSEMI,
314 .dev_id = 0xc42f,
315 .param = param_oxford,
316 },
317 /* OXPCIe200 1 Native UART */
318 {
319 .vendor_id = PCI_VENDOR_ID_OXSEMI,
320 .dev_id = 0xc43b,
321 .param = param_oxford,
322 },
323 /* OXPCIe200 1 Native UART */
324 {
325 .vendor_id = PCI_VENDOR_ID_OXSEMI,
326 .dev_id = 0xc43f,
327 .param = param_oxford,
328 },
329 /* OXPCIe200 1 Native UART */
330 {
331 .vendor_id = PCI_VENDOR_ID_OXSEMI,
332 .dev_id = 0xc44b,
333 .param = param_oxford,
334 },
335 /* OXPCIe200 1 Native UART */
336 {
337 .vendor_id = PCI_VENDOR_ID_OXSEMI,
338 .dev_id = 0xc44f,
339 .param = param_oxford,
340 },
341 /* OXPCIe200 1 Native UART */
342 {
343 .vendor_id = PCI_VENDOR_ID_OXSEMI,
344 .dev_id = 0xc45b,
345 .param = param_oxford,
346 },
347 /* OXPCIe200 1 Native UART */
348 {
349 .vendor_id = PCI_VENDOR_ID_OXSEMI,
350 .dev_id = 0xc45f,
351 .param = param_oxford,
352 },
353 /* OXPCIe200 1 Native UART */
354 {
355 .vendor_id = PCI_VENDOR_ID_OXSEMI,
356 .dev_id = 0xc46b,
357 .param = param_oxford,
358 },
359 /* OXPCIe200 1 Native UART */
360 {
361 .vendor_id = PCI_VENDOR_ID_OXSEMI,
362 .dev_id = 0xc46f,
363 .param = param_oxford,
364 },
365 /* OXPCIe200 1 Native UART */
366 {
367 .vendor_id = PCI_VENDOR_ID_OXSEMI,
368 .dev_id = 0xc47b,
369 .param = param_oxford,
370 },
371 /* OXPCIe200 1 Native UART */
372 {
373 .vendor_id = PCI_VENDOR_ID_OXSEMI,
374 .dev_id = 0xc47f,
375 .param = param_oxford,
376 },
377 /* OXPCIe200 1 Native UART */
378 {
379 .vendor_id = PCI_VENDOR_ID_OXSEMI,
380 .dev_id = 0xc48b,
381 .param = param_oxford,
382 },
383 /* OXPCIe200 1 Native UART */
384 {
385 .vendor_id = PCI_VENDOR_ID_OXSEMI,
386 .dev_id = 0xc48f,
387 .param = param_oxford,
388 },
389 /* OXPCIe200 1 Native UART */
390 {
391 .vendor_id = PCI_VENDOR_ID_OXSEMI,
392 .dev_id = 0xc49b,
393 .param = param_oxford,
394 },
395 /* OXPCIe200 1 Native UART */
396 {
397 .vendor_id = PCI_VENDOR_ID_OXSEMI,
398 .dev_id = 0xc49f,
399 .param = param_oxford,
400 },
401 /* OXPCIe200 1 Native UART */
402 {
403 .vendor_id = PCI_VENDOR_ID_OXSEMI,
404 .dev_id = 0xc4ab,
405 .param = param_oxford,
406 },
407 /* OXPCIe200 1 Native UART */
408 {
409 .vendor_id = PCI_VENDOR_ID_OXSEMI,
410 .dev_id = 0xc4af,
411 .param = param_oxford,
412 },
413 /* OXPCIe200 1 Native UART */
414 {
415 .vendor_id = PCI_VENDOR_ID_OXSEMI,
416 .dev_id = 0xc4bb,
417 .param = param_oxford,
418 },
419 /* OXPCIe200 1 Native UART */
420 {
421 .vendor_id = PCI_VENDOR_ID_OXSEMI,
422 .dev_id = 0xc4bf,
423 .param = param_oxford,
424 },
425 /* OXPCIe200 1 Native UART */
426 {
427 .vendor_id = PCI_VENDOR_ID_OXSEMI,
428 .dev_id = 0xc4cb,
429 .param = param_oxford,
430 },
431 /* OXPCIe200 1 Native UART */
432 {
433 .vendor_id = PCI_VENDOR_ID_OXSEMI,
434 .dev_id = 0xc4cf,
435 .param = param_oxford,
436 },
437 /* Pericom PI7C9X7951 Uno UART */
438 {
439 .vendor_id = PCI_VENDOR_ID_PERICOM,
440 .dev_id = 0x7951,
441 .param = param_pericom_1port
442 },
443 /* Pericom PI7C9X7952 Duo UART */
444 {
445 .vendor_id = PCI_VENDOR_ID_PERICOM,
446 .dev_id = 0x7952,
447 .param = param_pericom_2port
448 },
449 /* Pericom PI7C9X7954 Quad UART */
450 {
451 .vendor_id = PCI_VENDOR_ID_PERICOM,
452 .dev_id = 0x7954,
453 .param = param_pericom_4port
454 },
455 /* Pericom PI7C9X7958 Octal UART */
456 {
457 .vendor_id = PCI_VENDOR_ID_PERICOM,
458 .dev_id = 0x7958,
459 .param = param_pericom_8port
460 }
461 };
462 #endif
463
464 static void ns16550_delayed_resume(void *data);
465
ns_read_reg(struct ns16550 * uart,unsigned int reg)466 static u8 ns_read_reg(struct ns16550 *uart, unsigned int reg)
467 {
468 void __iomem *addr = uart->remapped_io_base + (reg << uart->reg_shift);
469 #ifdef CONFIG_HAS_IOPORTS
470 if ( uart->remapped_io_base == NULL )
471 return inb(uart->io_base + reg);
472 #endif
473 switch ( uart->reg_width )
474 {
475 case 1:
476 return readb(addr);
477 case 4:
478 return readl(addr);
479 default:
480 return 0xff;
481 }
482 }
483
ns_write_reg(struct ns16550 * uart,unsigned int reg,u8 c)484 static void ns_write_reg(struct ns16550 *uart, unsigned int reg, u8 c)
485 {
486 void __iomem *addr = uart->remapped_io_base + (reg << uart->reg_shift);
487 #ifdef CONFIG_HAS_IOPORTS
488 if ( uart->remapped_io_base == NULL )
489 return outb(c, uart->io_base + reg);
490 #endif
491 switch ( uart->reg_width )
492 {
493 case 1:
494 writeb(c, addr);
495 break;
496 case 4:
497 writel(c, addr);
498 break;
499 default:
500 /* Ignored */
501 break;
502 }
503 }
504
ns16550_ioport_invalid(struct ns16550 * uart)505 static int ns16550_ioport_invalid(struct ns16550 *uart)
506 {
507 return ns_read_reg(uart, UART_IER) == 0xff;
508 }
509
handle_dw_usr_busy_quirk(struct ns16550 * uart)510 static void handle_dw_usr_busy_quirk(struct ns16550 *uart)
511 {
512 if ( uart->dw_usr_bsy &&
513 (ns_read_reg(uart, UART_IIR) & UART_IIR_BSY) == UART_IIR_BSY )
514 {
515 /* DesignWare 8250 detects if LCR is written while the UART is
516 * busy and raises a "busy detect" interrupt. Read the UART
517 * Status Register to clear this state.
518 *
519 * Allwinner/sunxi UART hardware is similar to DesignWare 8250
520 * and also contains a "busy detect" interrupt. So this quirk
521 * fix will also be used for Allwinner UART.
522 */
523 ns_read_reg(uart, UART_USR);
524 }
525 }
526
ns16550_interrupt(int irq,void * dev_id,struct cpu_user_regs * regs)527 static void ns16550_interrupt(
528 int irq, void *dev_id, struct cpu_user_regs *regs)
529 {
530 struct serial_port *port = dev_id;
531 struct ns16550 *uart = port->uart;
532
533 uart->intr_works = 1;
534
535 while ( !(ns_read_reg(uart, UART_IIR) & UART_IIR_NOINT) )
536 {
537 u8 lsr = ns_read_reg(uart, UART_LSR);
538
539 if ( (lsr & uart->lsr_mask) == uart->lsr_mask )
540 serial_tx_interrupt(port, regs);
541 if ( lsr & UART_LSR_DR )
542 serial_rx_interrupt(port, regs);
543
544 /* A "busy-detect" condition is observed on Allwinner/sunxi UART
545 * after LCR is written during setup. It needs to be cleared at
546 * this point or UART_IIR_NOINT will never be set and this loop
547 * will continue forever.
548 *
549 * This state can be cleared by calling the dw_usr_busy quirk
550 * handler that resolves "busy-detect" for DesignWare uart.
551 */
552 handle_dw_usr_busy_quirk(uart);
553 }
554 }
555
556 /* Safe: ns16550_poll() runs as softirq so not reentrant on a given CPU. */
557 static DEFINE_PER_CPU(struct serial_port *, poll_port);
558
__ns16550_poll(struct cpu_user_regs * regs)559 static void __ns16550_poll(struct cpu_user_regs *regs)
560 {
561 struct serial_port *port = this_cpu(poll_port);
562 struct ns16550 *uart = port->uart;
563
564 if ( uart->intr_works )
565 return; /* Interrupts work - no more polling */
566
567 while ( ns_read_reg(uart, UART_LSR) & UART_LSR_DR )
568 {
569 if ( ns16550_ioport_invalid(uart) )
570 goto out;
571
572 serial_rx_interrupt(port, regs);
573 }
574
575 if ( ( ns_read_reg(uart, UART_LSR) & uart->lsr_mask ) == uart->lsr_mask )
576 serial_tx_interrupt(port, regs);
577
578 out:
579 set_timer(&uart->timer, NOW() + MILLISECS(uart->timeout_ms));
580 }
581
ns16550_poll(void * data)582 static void ns16550_poll(void *data)
583 {
584 this_cpu(poll_port) = data;
585 #ifdef run_in_exception_handler
586 run_in_exception_handler(__ns16550_poll);
587 #else
588 __ns16550_poll(guest_cpu_user_regs());
589 #endif
590 }
591
ns16550_tx_ready(struct serial_port * port)592 static int ns16550_tx_ready(struct serial_port *port)
593 {
594 struct ns16550 *uart = port->uart;
595
596 if ( ns16550_ioport_invalid(uart) )
597 return -EIO;
598
599 return ( (ns_read_reg(uart, UART_LSR) &
600 uart->lsr_mask ) == uart->lsr_mask ) ? uart->fifo_size : 0;
601 }
602
ns16550_putc(struct serial_port * port,char c)603 static void ns16550_putc(struct serial_port *port, char c)
604 {
605 struct ns16550 *uart = port->uart;
606 ns_write_reg(uart, UART_THR, c);
607 }
608
ns16550_getc(struct serial_port * port,char * pc)609 static int ns16550_getc(struct serial_port *port, char *pc)
610 {
611 struct ns16550 *uart = port->uart;
612
613 if ( ns16550_ioport_invalid(uart) ||
614 !(ns_read_reg(uart, UART_LSR) & UART_LSR_DR) )
615 return 0;
616
617 *pc = ns_read_reg(uart, UART_RBR);
618 return 1;
619 }
620
pci_serial_early_init(struct ns16550 * uart)621 static void pci_serial_early_init(struct ns16550 *uart)
622 {
623 #ifdef CONFIG_HAS_PCI
624 if ( !uart->ps_bdf_enable || uart->io_base >= 0x10000 )
625 return;
626
627 if ( uart->pb_bdf_enable )
628 pci_conf_write16(PCI_SBDF(0, uart->pb_bdf[0], uart->pb_bdf[1],
629 uart->pb_bdf[2]),
630 PCI_IO_BASE,
631 (uart->io_base & 0xF000) |
632 ((uart->io_base & 0xF000) >> 8));
633
634 pci_conf_write32(PCI_SBDF(0, uart->ps_bdf[0], uart->ps_bdf[1],
635 uart->ps_bdf[2]),
636 PCI_BASE_ADDRESS_0,
637 uart->io_base | PCI_BASE_ADDRESS_SPACE_IO);
638 pci_conf_write16(PCI_SBDF(0, uart->ps_bdf[0], uart->ps_bdf[1],
639 uart->ps_bdf[2]),
640 PCI_COMMAND, PCI_COMMAND_IO);
641 #endif
642 }
643
ns16550_setup_preirq(struct ns16550 * uart)644 static void ns16550_setup_preirq(struct ns16550 *uart)
645 {
646 unsigned char lcr;
647 unsigned int divisor;
648
649 uart->intr_works = 0;
650
651 pci_serial_early_init(uart);
652
653 lcr = (uart->data_bits - 5) | ((uart->stop_bits - 1) << 2) | uart->parity;
654
655 /* No interrupts. */
656 ns_write_reg(uart, UART_IER, 0);
657
658 /* Handle the DesignWare 8250 'busy-detect' quirk. */
659 handle_dw_usr_busy_quirk(uart);
660
661 /* Line control and baud-rate generator. */
662 ns_write_reg(uart, UART_LCR, lcr | UART_LCR_DLAB);
663 if ( uart->baud != BAUD_AUTO )
664 {
665 /* Baud rate specified: program it into the divisor latch. */
666 divisor = uart->clock_hz / (uart->baud << 4);
667 ns_write_reg(uart, UART_DLL, (char)divisor);
668 ns_write_reg(uart, UART_DLM, (char)(divisor >> 8));
669 }
670 else
671 {
672 /* Baud rate already set: read it out from the divisor latch. */
673 divisor = ns_read_reg(uart, UART_DLL);
674 divisor |= ns_read_reg(uart, UART_DLM) << 8;
675 if ( divisor )
676 uart->baud = uart->clock_hz / (divisor << 4);
677 else
678 printk(XENLOG_ERR
679 "Automatic baud rate determination was requested,"
680 " but a baud rate was not set up\n");
681 }
682 ns_write_reg(uart, UART_LCR, lcr);
683
684 /* No flow ctrl: DTR and RTS are both wedged high to keep remote happy. */
685 ns_write_reg(uart, UART_MCR, UART_MCR_DTR | UART_MCR_RTS);
686
687 /* Enable and clear the FIFOs. Set a large trigger threshold. */
688 ns_write_reg(uart, UART_FCR,
689 UART_FCR_ENABLE | UART_FCR_CLRX | UART_FCR_CLTX | UART_FCR_TRG14);
690 }
691
ns16550_init_preirq(struct serial_port * port)692 static void __init ns16550_init_preirq(struct serial_port *port)
693 {
694 struct ns16550 *uart = port->uart;
695
696 #ifdef CONFIG_HAS_IOPORTS
697 /* I/O ports are distinguished by their size (16 bits). */
698 if ( uart->io_base >= 0x10000 )
699 #endif
700 {
701 #ifdef CONFIG_X86
702 enum fixed_addresses idx = FIX_COM_BEGIN + (uart - ns16550_com);
703
704 set_fixmap_nocache(idx, uart->io_base);
705 uart->remapped_io_base = fix_to_virt(idx);
706 uart->remapped_io_base += uart->io_base & ~PAGE_MASK;
707 #else
708 uart->remapped_io_base = (char *)ioremap(uart->io_base, uart->io_size);
709 #endif
710 }
711
712 ns16550_setup_preirq(uart);
713
714 /* Check this really is a 16550+. Otherwise we have no FIFOs. */
715 if ( ((ns_read_reg(uart, UART_IIR) & 0xc0) == 0xc0) &&
716 ((ns_read_reg(uart, UART_FCR) & UART_FCR_TRG14) == UART_FCR_TRG14) )
717 uart->fifo_size = 16;
718 }
719
ns16550_init_irq(struct serial_port * port)720 static void __init ns16550_init_irq(struct serial_port *port)
721 {
722 #ifdef CONFIG_HAS_PCI
723 struct ns16550 *uart = port->uart;
724
725 if ( uart->msi )
726 uart->irq = create_irq(0, false);
727 #endif
728 }
729
ns16550_setup_postirq(struct ns16550 * uart)730 static void ns16550_setup_postirq(struct ns16550 *uart)
731 {
732 if ( uart->irq > 0 )
733 {
734 /* Master interrupt enable; also keep DTR/RTS asserted. */
735 ns_write_reg(uart,
736 UART_MCR, UART_MCR_OUT2 | UART_MCR_DTR | UART_MCR_RTS);
737
738 /* Enable receive interrupts. */
739 ns_write_reg(uart, UART_IER, UART_IER_ERDAI);
740 }
741
742 if ( uart->irq >= 0 )
743 set_timer(&uart->timer, NOW() + MILLISECS(uart->timeout_ms));
744 }
745
ns16550_init_postirq(struct serial_port * port)746 static void __init ns16550_init_postirq(struct serial_port *port)
747 {
748 struct ns16550 *uart = port->uart;
749 int rc, bits;
750
751 if ( uart->irq < 0 )
752 return;
753
754 serial_async_transmit(port);
755
756 init_timer(&uart->timer, ns16550_poll, port, 0);
757 init_timer(&uart->resume_timer, ns16550_delayed_resume, port, 0);
758
759 /* Calculate time to fill RX FIFO and/or empty TX FIFO for polling. */
760 bits = uart->data_bits + uart->stop_bits + !!uart->parity;
761 uart->timeout_ms = max_t(
762 unsigned int, 1, (bits * uart->fifo_size * 1000) / uart->baud);
763
764 #ifdef CONFIG_HAS_PCI
765 if ( uart->bar || uart->ps_bdf_enable )
766 {
767 if ( uart->param && uart->param->mmio &&
768 rangeset_add_range(mmio_ro_ranges, uart->io_base,
769 uart->io_base + uart->io_size - 1) )
770 printk(XENLOG_INFO "Error while adding MMIO range of device to mmio_ro_ranges\n");
771
772 if ( pci_ro_device(0, uart->ps_bdf[0],
773 PCI_DEVFN(uart->ps_bdf[1], uart->ps_bdf[2])) )
774 printk(XENLOG_INFO "Could not mark config space of %02x:%02x.%u read-only.\n",
775 uart->ps_bdf[0], uart->ps_bdf[1],
776 uart->ps_bdf[2]);
777
778 if ( uart->msi )
779 {
780 struct msi_info msi = {
781 .bus = uart->ps_bdf[0],
782 .devfn = PCI_DEVFN(uart->ps_bdf[1], uart->ps_bdf[2]),
783 .irq = rc = uart->irq,
784 .entry_nr = 1
785 };
786
787 if ( rc > 0 )
788 {
789 struct msi_desc *msi_desc = NULL;
790
791 pcidevs_lock();
792
793 rc = pci_enable_msi(&msi, &msi_desc);
794 if ( !rc )
795 {
796 struct irq_desc *desc = irq_to_desc(msi.irq);
797 unsigned long flags;
798
799 spin_lock_irqsave(&desc->lock, flags);
800 rc = setup_msi_irq(desc, msi_desc);
801 spin_unlock_irqrestore(&desc->lock, flags);
802 if ( rc )
803 pci_disable_msi(msi_desc);
804 }
805
806 pcidevs_unlock();
807
808 if ( rc )
809 {
810 uart->irq = 0;
811 if ( msi_desc )
812 msi_free_irq(msi_desc);
813 else
814 destroy_irq(msi.irq);
815 }
816 }
817
818 if ( rc )
819 printk(XENLOG_WARNING
820 "MSI setup failed (%d) for %02x:%02x.%o\n",
821 rc, uart->ps_bdf[0], uart->ps_bdf[1], uart->ps_bdf[2]);
822 }
823 }
824 #endif
825
826 if ( uart->irq > 0 )
827 {
828 uart->irqaction.handler = ns16550_interrupt;
829 uart->irqaction.name = "ns16550";
830 uart->irqaction.dev_id = port;
831 if ( (rc = setup_irq(uart->irq, 0, &uart->irqaction)) != 0 )
832 printk("ERROR: Failed to allocate ns16550 IRQ %d\n", uart->irq);
833 }
834
835 ns16550_setup_postirq(uart);
836 }
837
ns16550_suspend(struct serial_port * port)838 static void ns16550_suspend(struct serial_port *port)
839 {
840 struct ns16550 *uart = port->uart;
841
842 stop_timer(&uart->timer);
843
844 #ifdef CONFIG_HAS_PCI
845 if ( uart->bar )
846 uart->cr = pci_conf_read16(PCI_SBDF(0, uart->ps_bdf[0], uart->ps_bdf[1],
847 uart->ps_bdf[2]), PCI_COMMAND);
848 #endif
849 }
850
_ns16550_resume(struct serial_port * port)851 static void _ns16550_resume(struct serial_port *port)
852 {
853 #ifdef CONFIG_HAS_PCI
854 struct ns16550 *uart = port->uart;
855
856 if ( uart->bar )
857 {
858 pci_conf_write32(PCI_SBDF(0, uart->ps_bdf[0], uart->ps_bdf[1],
859 uart->ps_bdf[2]),
860 PCI_BASE_ADDRESS_0 + uart->bar_idx*4, uart->bar);
861
862 /* If 64 bit BAR, write higher 32 bits to BAR+4 */
863 if ( uart->bar & PCI_BASE_ADDRESS_MEM_TYPE_64 )
864 pci_conf_write32(PCI_SBDF(0, uart->ps_bdf[0], uart->ps_bdf[1],
865 uart->ps_bdf[2]),
866 PCI_BASE_ADDRESS_0 + (uart->bar_idx+1)*4, uart->bar64);
867
868 pci_conf_write16(PCI_SBDF(0, uart->ps_bdf[0], uart->ps_bdf[1],
869 uart->ps_bdf[2]),
870 PCI_COMMAND, uart->cr);
871 }
872 #endif
873
874 ns16550_setup_preirq(port->uart);
875 ns16550_setup_postirq(port->uart);
876 }
877
878 static int delayed_resume_tries;
ns16550_delayed_resume(void * data)879 static void ns16550_delayed_resume(void *data)
880 {
881 struct serial_port *port = data;
882 struct ns16550 *uart = port->uart;
883
884 if ( ns16550_ioport_invalid(port->uart) && delayed_resume_tries-- )
885 set_timer(&uart->resume_timer, NOW() + RESUME_DELAY);
886 else
887 _ns16550_resume(port);
888 }
889
ns16550_resume(struct serial_port * port)890 static void ns16550_resume(struct serial_port *port)
891 {
892 struct ns16550 *uart = port->uart;
893
894 /*
895 * Check for ioport access, before fully resuming operation.
896 * On some systems, there is a SuperIO card that provides
897 * this legacy ioport on the LPC bus.
898 *
899 * We need to wait for dom0's ACPI processing to run the proper
900 * AML to re-initialize the chip, before we can use the card again.
901 *
902 * This may cause a small amount of garbage to be written
903 * to the serial log while we wait patiently for that AML to
904 * be executed. However, this is preferable to spinning in an
905 * infinite loop, as seen on a Lenovo T430, when serial was enabled.
906 */
907 if ( ns16550_ioport_invalid(uart) )
908 {
909 delayed_resume_tries = RESUME_RETRIES;
910 set_timer(&uart->resume_timer, NOW() + RESUME_DELAY);
911 }
912 else
913 _ns16550_resume(port);
914 }
915
ns16550_endboot(struct serial_port * port)916 static void __init ns16550_endboot(struct serial_port *port)
917 {
918 #ifdef CONFIG_HAS_IOPORTS
919 struct ns16550 *uart = port->uart;
920 int rv;
921
922 if ( uart->remapped_io_base )
923 return;
924 rv = ioports_deny_access(hardware_domain, uart->io_base, uart->io_base + 7);
925 if ( rv != 0 )
926 BUG();
927 #endif
928 }
929
ns16550_irq(struct serial_port * port)930 static int __init ns16550_irq(struct serial_port *port)
931 {
932 struct ns16550 *uart = port->uart;
933 return ((uart->irq > 0) ? uart->irq : -1);
934 }
935
ns16550_start_tx(struct serial_port * port)936 static void ns16550_start_tx(struct serial_port *port)
937 {
938 struct ns16550 *uart = port->uart;
939 u8 ier = ns_read_reg(uart, UART_IER);
940
941 /* Unmask transmit holding register empty interrupt if currently masked. */
942 if ( !(ier & UART_IER_ETHREI) )
943 ns_write_reg(uart, UART_IER, ier | UART_IER_ETHREI);
944 }
945
ns16550_stop_tx(struct serial_port * port)946 static void ns16550_stop_tx(struct serial_port *port)
947 {
948 struct ns16550 *uart = port->uart;
949 u8 ier = ns_read_reg(uart, UART_IER);
950
951 /* Mask off transmit holding register empty interrupt if currently unmasked. */
952 if ( ier & UART_IER_ETHREI )
953 ns_write_reg(uart, UART_IER, ier & ~UART_IER_ETHREI);
954 }
955
956 #ifdef CONFIG_ARM
ns16550_vuart_info(struct serial_port * port)957 static const struct vuart_info *ns16550_vuart_info(struct serial_port *port)
958 {
959 struct ns16550 *uart = port->uart;
960
961 return &uart->vuart;
962 }
963 #endif
964
965 static struct uart_driver __read_mostly ns16550_driver = {
966 .init_preirq = ns16550_init_preirq,
967 .init_irq = ns16550_init_irq,
968 .init_postirq = ns16550_init_postirq,
969 .endboot = ns16550_endboot,
970 .suspend = ns16550_suspend,
971 .resume = ns16550_resume,
972 .tx_ready = ns16550_tx_ready,
973 .putc = ns16550_putc,
974 .getc = ns16550_getc,
975 .irq = ns16550_irq,
976 .start_tx = ns16550_start_tx,
977 .stop_tx = ns16550_stop_tx,
978 #ifdef CONFIG_ARM
979 .vuart_info = ns16550_vuart_info,
980 #endif
981 };
982
parse_parity_char(int c)983 static int __init parse_parity_char(int c)
984 {
985 switch ( c )
986 {
987 case 'n':
988 return UART_PARITY_NONE;
989 case 'o':
990 return UART_PARITY_ODD;
991 case 'e':
992 return UART_PARITY_EVEN;
993 case 'm':
994 return UART_PARITY_MARK;
995 case 's':
996 return UART_PARITY_SPACE;
997 }
998 return 0;
999 }
1000
check_existence(struct ns16550 * uart)1001 static int __init check_existence(struct ns16550 *uart)
1002 {
1003 unsigned char status, scratch, scratch2, scratch3;
1004
1005 #ifdef CONFIG_HAS_IOPORTS
1006 /*
1007 * We can't poke MMIO UARTs until they get I/O remapped later. Assume that
1008 * if we're getting MMIO UARTs, the arch code knows what it's doing.
1009 */
1010 if ( uart->io_base >= 0x10000 )
1011 return 1;
1012 #else
1013 return 1; /* Everything is MMIO */
1014 #endif
1015
1016 #ifdef CONFIG_HAS_PCI
1017 pci_serial_early_init(uart);
1018 #endif
1019
1020 /*
1021 * Do a simple existence test first; if we fail this,
1022 * there's no point trying anything else.
1023 */
1024 scratch = ns_read_reg(uart, UART_IER);
1025 ns_write_reg(uart, UART_IER, 0);
1026
1027 /*
1028 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1029 * 16C754B) allow only to modify them if an EFR bit is set.
1030 */
1031 scratch2 = ns_read_reg(uart, UART_IER) & 0x0f;
1032 ns_write_reg(uart,UART_IER, 0x0F);
1033 scratch3 = ns_read_reg(uart, UART_IER) & 0x0f;
1034 ns_write_reg(uart, UART_IER, scratch);
1035 if ( (scratch2 != 0) || (scratch3 != 0x0F) )
1036 return 0;
1037
1038 /*
1039 * Check to see if a UART is really there.
1040 * Use loopback test mode.
1041 */
1042 ns_write_reg(uart, UART_MCR, UART_MCR_LOOP | 0x0A);
1043 status = ns_read_reg(uart, UART_MSR) & 0xF0;
1044 return (status == 0x90);
1045 }
1046
1047 #ifdef CONFIG_HAS_PCI
1048 static int __init
pci_uart_config(struct ns16550 * uart,bool_t skip_amt,unsigned int idx)1049 pci_uart_config(struct ns16550 *uart, bool_t skip_amt, unsigned int idx)
1050 {
1051 u64 orig_base = uart->io_base;
1052 unsigned int b, d, f, nextf, i;
1053
1054 /* NB. Start at bus 1 to avoid AMT: a plug-in card cannot be on bus 0. */
1055 for ( b = skip_amt ? 1 : 0; b < 0x100; b++ )
1056 {
1057 for ( d = 0; d < 0x20; d++ )
1058 {
1059 for ( f = 0; f < 8; f = nextf )
1060 {
1061 unsigned int bar_idx = 0, port_idx = idx;
1062 uint32_t bar, bar_64 = 0, len, len_64;
1063 u64 size = 0;
1064 const struct ns16550_config_param *param = uart_param;
1065
1066 nextf = (f || (pci_conf_read16(PCI_SBDF(0, b, d, f),
1067 PCI_HEADER_TYPE) &
1068 0x80)) ? f + 1 : 8;
1069
1070 switch ( pci_conf_read16(PCI_SBDF(0, b, d, f),
1071 PCI_CLASS_DEVICE) )
1072 {
1073 case 0x0700: /* single port serial */
1074 case 0x0702: /* multi port serial */
1075 case 0x0780: /* other (e.g serial+parallel) */
1076 break;
1077 case 0xffff:
1078 if ( !f )
1079 nextf = 8;
1080 /* fall through */
1081 default:
1082 continue;
1083 }
1084
1085 /* Check for params in uart_config lookup table */
1086 for ( i = 0; i < ARRAY_SIZE(uart_config); i++ )
1087 {
1088 u16 vendor = pci_conf_read16(PCI_SBDF(0, b, d, f),
1089 PCI_VENDOR_ID);
1090 u16 device = pci_conf_read16(PCI_SBDF(0, b, d, f),
1091 PCI_DEVICE_ID);
1092
1093 if ( uart_config[i].vendor_id == vendor &&
1094 uart_config[i].dev_id == device )
1095 {
1096 param += uart_config[i].param;
1097 break;
1098 }
1099 }
1100
1101 if ( port_idx >= param->max_ports )
1102 {
1103 idx -= param->max_ports;
1104 continue;
1105 }
1106
1107 if ( !param->bar0 )
1108 {
1109 bar_idx = idx;
1110 port_idx = 0;
1111 }
1112
1113 uart->io_base = 0;
1114 bar = pci_conf_read32(PCI_SBDF(0, b, d, f),
1115 PCI_BASE_ADDRESS_0 + bar_idx * 4);
1116
1117 /* MMIO based */
1118 if ( param->mmio && !(bar & PCI_BASE_ADDRESS_SPACE_IO) )
1119 {
1120 pci_conf_write32(PCI_SBDF(0, b, d, f),
1121 PCI_BASE_ADDRESS_0 + bar_idx*4, ~0u);
1122 len = pci_conf_read32(PCI_SBDF(0, b, d, f),
1123 PCI_BASE_ADDRESS_0 + bar_idx * 4);
1124 pci_conf_write32(PCI_SBDF(0, b, d, f),
1125 PCI_BASE_ADDRESS_0 + bar_idx*4, bar);
1126
1127 /* Handle 64 bit BAR if found */
1128 if ( bar & PCI_BASE_ADDRESS_MEM_TYPE_64 )
1129 {
1130 bar_64 = pci_conf_read32(PCI_SBDF(0, b, d, f),
1131 PCI_BASE_ADDRESS_0 + (bar_idx + 1) * 4);
1132 pci_conf_write32(PCI_SBDF(0, b, d, f),
1133 PCI_BASE_ADDRESS_0 + (bar_idx+1)*4, ~0u);
1134 len_64 = pci_conf_read32(PCI_SBDF(0, b, d, f),
1135 PCI_BASE_ADDRESS_0 + (bar_idx + 1) * 4);
1136 pci_conf_write32(PCI_SBDF(0, b, d, f),
1137 PCI_BASE_ADDRESS_0 + (bar_idx+1)*4, bar_64);
1138 size = ((u64)~0 << 32) | PCI_BASE_ADDRESS_MEM_MASK;
1139 size &= ((u64)len_64 << 32) | len;
1140 }
1141 else
1142 size = len & PCI_BASE_ADDRESS_MEM_MASK;
1143
1144 uart->io_base = ((u64)bar_64 << 32) |
1145 (bar & PCI_BASE_ADDRESS_MEM_MASK);
1146 }
1147 /* IO based */
1148 else if ( !param->mmio && (bar & PCI_BASE_ADDRESS_SPACE_IO) )
1149 {
1150 pci_conf_write32(PCI_SBDF(0, b, d, f),
1151 PCI_BASE_ADDRESS_0 + bar_idx*4, ~0u);
1152 len = pci_conf_read32(PCI_SBDF(0, b, d, f),
1153 PCI_BASE_ADDRESS_0);
1154 pci_conf_write32(PCI_SBDF(0, b, d, f),
1155 PCI_BASE_ADDRESS_0 + bar_idx*4, bar);
1156 size = len & PCI_BASE_ADDRESS_IO_MASK;
1157
1158 uart->io_base = bar & ~PCI_BASE_ADDRESS_SPACE_IO;
1159 }
1160
1161 /* If we have an io_base, then we succeeded in the lookup. */
1162 if ( !uart->io_base )
1163 continue;
1164
1165 size &= -size;
1166
1167 /*
1168 * Require length of actually used region to be at least
1169 * 8 bytes times (1 << reg_shift).
1170 */
1171 if ( size < param->first_offset +
1172 port_idx * param->uart_offset +
1173 (8 << param->reg_shift) )
1174 continue;
1175
1176 uart->param = param;
1177
1178 uart->reg_shift = param->reg_shift;
1179 uart->reg_width = param->reg_width;
1180 uart->lsr_mask = param->lsr_mask;
1181 uart->io_base += param->first_offset +
1182 port_idx * param->uart_offset;
1183 if ( param->base_baud )
1184 uart->clock_hz = param->base_baud * 16;
1185 if ( param->fifo_size )
1186 uart->fifo_size = param->fifo_size;
1187
1188 uart->ps_bdf[0] = b;
1189 uart->ps_bdf[1] = d;
1190 uart->ps_bdf[2] = f;
1191 uart->bar_idx = bar_idx;
1192 uart->bar = bar;
1193 uart->bar64 = bar_64;
1194 uart->io_size = max(8U << param->reg_shift,
1195 param->uart_offset);
1196 uart->irq = pci_conf_read8(PCI_SBDF(0, b, d, f),
1197 PCI_INTERRUPT_PIN) ?
1198 pci_conf_read8(PCI_SBDF(0, b, d, f),
1199 PCI_INTERRUPT_LINE) : 0;
1200
1201 return 0;
1202 }
1203 }
1204 }
1205
1206 if ( !skip_amt )
1207 return -1;
1208
1209 /* No AMT found, fallback to the defaults. */
1210 uart->io_base = orig_base;
1211
1212 return 0;
1213 }
1214 #endif
1215
1216 /*
1217 * Used to parse name value pairs and return which value it is along with
1218 * pointer for the extracted value.
1219 */
get_token(char * token,char ** value)1220 static enum __init serial_param_type get_token(char *token, char **value)
1221 {
1222 const char *param_name;
1223 unsigned int i;
1224
1225 param_name = strsep(&token, "=");
1226 if ( param_name == NULL )
1227 return num_serial_params;
1228
1229 /* Linear search for the parameter. */
1230 for ( i = 0; i < ARRAY_SIZE(sp_vars); i++ )
1231 {
1232 if ( strcmp(sp_vars[i].name, param_name) == 0 )
1233 {
1234 *value = token;
1235 return sp_vars[i].type;
1236 }
1237 }
1238
1239 return num_serial_params;
1240 }
1241
1242 #define PARSE_ERR(_f, _a...) \
1243 do { \
1244 printk( "ERROR: " _f "\n" , ## _a ); \
1245 return; \
1246 } while ( 0 )
1247
1248 #define PARSE_ERR_RET(_f, _a...) \
1249 do { \
1250 printk( "ERROR: " _f "\n" , ## _a ); \
1251 return false; \
1252 } while ( 0 )
1253
1254
parse_positional(struct ns16550 * uart,char ** str)1255 static bool __init parse_positional(struct ns16550 *uart, char **str)
1256 {
1257 int baud;
1258 const char *conf;
1259 char *name_val_pos;
1260
1261 conf = *str;
1262 name_val_pos = strchr(conf, '=');
1263
1264 /* Finding the end of the positional parameters. */
1265 while ( name_val_pos > *str )
1266 {
1267 /* Working backwards from the '=' sign. */
1268 name_val_pos--;
1269 if ( *name_val_pos == ',' )
1270 {
1271 *name_val_pos = '\0';
1272 name_val_pos++;
1273 break;
1274 }
1275 }
1276
1277 *str = name_val_pos;
1278 /* When there are no positional parameters, we return from the function. */
1279 if ( conf == *str )
1280 return true;
1281
1282 /* Parse positional parameters here. */
1283 if ( strncmp(conf, "auto", 4) == 0 )
1284 {
1285 uart->baud = BAUD_AUTO;
1286 conf += 4;
1287 }
1288 else if ( (baud = simple_strtoul(conf, &conf, 10)) != 0 )
1289 uart->baud = baud;
1290
1291 if ( *conf == '/' )
1292 {
1293 conf++;
1294 uart->clock_hz = simple_strtoul(conf, &conf, 0) << 4;
1295 }
1296
1297 if ( *conf == ',' && *++conf != ',' )
1298 {
1299 uart->data_bits = simple_strtoul(conf, &conf, 10);
1300
1301 uart->parity = parse_parity_char(*conf);
1302
1303 uart->stop_bits = simple_strtoul(conf + 1, &conf, 10);
1304 }
1305
1306 if ( *conf == ',' && *++conf != ',' )
1307 {
1308 #ifdef CONFIG_HAS_PCI
1309 if ( strncmp(conf, "pci", 3) == 0 )
1310 {
1311 if ( pci_uart_config(uart, 1/* skip AMT */, uart - ns16550_com) )
1312 return true;
1313 conf += 3;
1314 }
1315 else if ( strncmp(conf, "amt", 3) == 0 )
1316 {
1317 if ( pci_uart_config(uart, 0, uart - ns16550_com) )
1318 return true;
1319 conf += 3;
1320 }
1321 else
1322 #endif
1323 {
1324 uart->io_base = simple_strtoul(conf, &conf, 0);
1325 }
1326 }
1327
1328 if ( *conf == ',' && *++conf != ',' )
1329 {
1330 #ifdef CONFIG_HAS_PCI
1331 if ( strncmp(conf, "msi", 3) == 0 )
1332 {
1333 conf += 3;
1334 uart->msi = true;
1335 uart->irq = 0;
1336 }
1337 else
1338 #endif
1339 uart->irq = simple_strtol(conf, &conf, 10);
1340 }
1341
1342 #ifdef CONFIG_HAS_PCI
1343 if ( *conf == ',' && *++conf != ',' )
1344 {
1345 conf = parse_pci(conf, NULL, &uart->ps_bdf[0],
1346 &uart->ps_bdf[1], &uart->ps_bdf[2]);
1347 if ( !conf )
1348 PARSE_ERR_RET("Bad port PCI coordinates");
1349 uart->ps_bdf_enable = true;
1350 }
1351
1352 if ( *conf == ',' && *++conf != ',' )
1353 {
1354 if ( !parse_pci(conf, NULL, &uart->pb_bdf[0],
1355 &uart->pb_bdf[1], &uart->pb_bdf[2]) )
1356 PARSE_ERR_RET("Bad bridge PCI coordinates");
1357 uart->pb_bdf_enable = true;
1358 }
1359 #endif
1360
1361 return true;
1362 }
1363
parse_namevalue_pairs(char * str,struct ns16550 * uart)1364 static bool __init parse_namevalue_pairs(char *str, struct ns16550 *uart)
1365 {
1366 char *token, *start = str;
1367 char *param_value = NULL;
1368 bool dev_set = false;
1369
1370 if ( (str == NULL) || (*str == '\0') )
1371 return true;
1372
1373 do
1374 {
1375 /* When no tokens are found, start will be NULL */
1376 token = strsep(&start, ",");
1377
1378 switch ( get_token(token, ¶m_value) )
1379 {
1380 case baud:
1381 uart->baud = simple_strtoul(param_value, NULL, 0);
1382 break;
1383
1384 case clock_hz:
1385 uart->clock_hz = simple_strtoul(param_value, NULL, 0) << 4;
1386 break;
1387
1388 case io_base:
1389 if ( dev_set )
1390 {
1391 printk(XENLOG_WARNING
1392 "Can't use io_base with dev=pci or dev=amt options\n");
1393 break;
1394 }
1395 uart->io_base = simple_strtoul(param_value, NULL, 0);
1396 break;
1397
1398 case irq:
1399 uart->irq = simple_strtoul(param_value, NULL, 0);
1400 break;
1401
1402 case data_bits:
1403 uart->data_bits = simple_strtoul(param_value, NULL, 0);
1404 break;
1405
1406 case parity:
1407 uart->parity = parse_parity_char(*param_value);
1408 break;
1409
1410 case stop_bits:
1411 uart->stop_bits = simple_strtoul(param_value, NULL, 0);
1412 break;
1413
1414 case reg_shift:
1415 uart->reg_shift = simple_strtoul(param_value, NULL, 0);
1416 break;
1417
1418 case reg_width:
1419 uart->reg_width = simple_strtoul(param_value, NULL, 0);
1420 break;
1421
1422 #ifdef CONFIG_HAS_PCI
1423 case bridge_bdf:
1424 if ( !parse_pci(param_value, NULL, &uart->ps_bdf[0],
1425 &uart->ps_bdf[1], &uart->ps_bdf[2]) )
1426 PARSE_ERR_RET("Bad port PCI coordinates\n");
1427 uart->ps_bdf_enable = true;
1428 break;
1429
1430 case device:
1431 if ( strncmp(param_value, "pci", 3) == 0 )
1432 {
1433 pci_uart_config(uart, 1/* skip AMT */, uart - ns16550_com);
1434 dev_set = true;
1435 }
1436 else if ( strncmp(param_value, "amt", 3) == 0 )
1437 {
1438 pci_uart_config(uart, 0, uart - ns16550_com);
1439 dev_set = true;
1440 }
1441 break;
1442
1443 case port_bdf:
1444 if ( !parse_pci(param_value, NULL, &uart->pb_bdf[0],
1445 &uart->pb_bdf[1], &uart->pb_bdf[2]) )
1446 PARSE_ERR_RET("Bad port PCI coordinates\n");
1447 uart->pb_bdf_enable = true;
1448 break;
1449 #endif
1450
1451 default:
1452 PARSE_ERR_RET("Invalid parameter: %s\n", token);
1453 }
1454 } while ( start != NULL );
1455
1456 return true;
1457 }
1458
ns16550_parse_port_config(struct ns16550 * uart,const char * conf)1459 static void __init ns16550_parse_port_config(
1460 struct ns16550 *uart, const char *conf)
1461 {
1462 char com_console_options[128];
1463 char *str;
1464
1465 /* No user-specified configuration? */
1466 if ( (conf == NULL) || (*conf == '\0') )
1467 {
1468 /* Some platforms may automatically probe the UART configuartion. */
1469 if ( uart->baud != 0 )
1470 goto config_parsed;
1471 return;
1472 }
1473
1474 strlcpy(com_console_options, conf, ARRAY_SIZE(com_console_options));
1475 str = com_console_options;
1476
1477 /* parse positional parameters and get pointer for name-value pairs */
1478 if ( !parse_positional(uart, &str) )
1479 return;
1480
1481 if ( !parse_namevalue_pairs(str, uart) )
1482 return;
1483
1484 config_parsed:
1485 /* Sanity checks. */
1486 if ( (uart->baud != BAUD_AUTO) &&
1487 ((uart->baud < 1200) || (uart->baud > 115200)) )
1488 PARSE_ERR("Baud rate %d outside supported range.", uart->baud);
1489 if ( (uart->data_bits < 5) || (uart->data_bits > 8) )
1490 PARSE_ERR("%d data bits are unsupported.", uart->data_bits);
1491 if ( (uart->reg_width != 1) && (uart->reg_width != 4) )
1492 PARSE_ERR("Accepted values of reg_width are 1 and 4 only");
1493 if ( (uart->stop_bits < 1) || (uart->stop_bits > 2) )
1494 PARSE_ERR("%d stop bits are unsupported.", uart->stop_bits);
1495 if ( uart->io_base == 0 )
1496 PARSE_ERR("I/O base address must be specified.");
1497 if ( !check_existence(uart) )
1498 PARSE_ERR("16550-compatible serial UART not present");
1499
1500 /* Register with generic serial driver. */
1501 serial_register_uart(uart - ns16550_com, &ns16550_driver, uart);
1502 }
1503
ns16550_init_common(struct ns16550 * uart)1504 static void ns16550_init_common(struct ns16550 *uart)
1505 {
1506 uart->clock_hz = UART_CLOCK_HZ;
1507
1508 /* Default is no transmit FIFO. */
1509 uart->fifo_size = 1;
1510
1511 /* Default lsr_mask = UART_LSR_THRE */
1512 uart->lsr_mask = UART_LSR_THRE;
1513 }
1514
ns16550_init(int index,struct ns16550_defaults * defaults)1515 void __init ns16550_init(int index, struct ns16550_defaults *defaults)
1516 {
1517 struct ns16550 *uart;
1518
1519 if ( (index < 0) || (index > 1) )
1520 return;
1521
1522 uart = &ns16550_com[index];
1523
1524 ns16550_init_common(uart);
1525
1526 uart->baud = (defaults->baud ? :
1527 console_has((index == 0) ? "com1" : "com2")
1528 ? BAUD_AUTO : 0);
1529 uart->data_bits = defaults->data_bits;
1530 uart->parity = parse_parity_char(defaults->parity);
1531 uart->stop_bits = defaults->stop_bits;
1532 uart->irq = defaults->irq;
1533 uart->io_base = defaults->io_base;
1534 uart->io_size = 8;
1535 uart->reg_width = 1;
1536 uart->reg_shift = 0;
1537
1538 ns16550_parse_port_config(uart, (index == 0) ? opt_com1 : opt_com2);
1539 }
1540
1541 #ifdef CONFIG_HAS_DEVICE_TREE
ns16550_uart_dt_init(struct dt_device_node * dev,const void * data)1542 static int __init ns16550_uart_dt_init(struct dt_device_node *dev,
1543 const void *data)
1544 {
1545 struct ns16550 *uart;
1546 int res;
1547 u32 reg_shift, reg_width;
1548 u64 io_size;
1549
1550 uart = &ns16550_com[0];
1551
1552 ns16550_init_common(uart);
1553
1554 uart->baud = BAUD_AUTO;
1555 uart->data_bits = 8;
1556 uart->parity = UART_PARITY_NONE;
1557 uart->stop_bits = 1;
1558
1559 res = dt_device_get_address(dev, 0, &uart->io_base, &io_size);
1560 if ( res )
1561 return res;
1562
1563 uart->io_size = io_size;
1564
1565 ASSERT(uart->io_size == io_size); /* Detect truncation */
1566
1567 res = dt_property_read_u32(dev, "reg-shift", ®_shift);
1568 if ( !res )
1569 uart->reg_shift = 0;
1570 else
1571 uart->reg_shift = reg_shift;
1572
1573 res = dt_property_read_u32(dev, "reg-io-width", ®_width);
1574 if ( !res )
1575 uart->reg_width = 1;
1576 else
1577 uart->reg_width = reg_width;
1578
1579 if ( uart->reg_width != 1 && uart->reg_width != 4 )
1580 return -EINVAL;
1581
1582 if ( dt_device_is_compatible(dev, "brcm,bcm2835-aux-uart") )
1583 {
1584 uart->reg_width = 4;
1585 uart->reg_shift = 2;
1586 }
1587
1588 res = platform_get_irq(dev, 0);
1589 if ( ! res )
1590 return -EINVAL;
1591 uart->irq = res;
1592
1593 uart->dw_usr_bsy = dt_device_is_compatible(dev, "snps,dw-apb-uart");
1594
1595 uart->vuart.base_addr = uart->io_base;
1596 uart->vuart.size = uart->io_size;
1597 uart->vuart.data_off = UART_THR <<uart->reg_shift;
1598 uart->vuart.status_off = UART_LSR<<uart->reg_shift;
1599 uart->vuart.status = UART_LSR_THRE|UART_LSR_TEMT;
1600
1601 /* Register with generic serial driver. */
1602 serial_register_uart(uart - ns16550_com, &ns16550_driver, uart);
1603
1604 dt_device_set_used_by(dev, DOMID_XEN);
1605
1606 return 0;
1607 }
1608
1609 static const struct dt_device_match ns16550_dt_match[] __initconst =
1610 {
1611 DT_MATCH_COMPATIBLE("ns16550"),
1612 DT_MATCH_COMPATIBLE("ns16550a"),
1613 DT_MATCH_COMPATIBLE("snps,dw-apb-uart"),
1614 DT_MATCH_COMPATIBLE("brcm,bcm2835-aux-uart"),
1615 { /* sentinel */ },
1616 };
1617
1618 DT_DEVICE_START(ns16550, "NS16550 UART", DEVICE_SERIAL)
1619 .dt_match = ns16550_dt_match,
1620 .init = ns16550_uart_dt_init,
1621 DT_DEVICE_END
1622
1623 #endif /* HAS_DEVICE_TREE */
1624
1625 #if defined(CONFIG_ACPI) && defined(CONFIG_ARM)
1626 #include <xen/acpi.h>
1627
1628 static int __init ns16550_acpi_uart_init(const void *data)
1629 {
1630 struct acpi_table_header *table;
1631 struct acpi_table_spcr *spcr;
1632 acpi_status status;
1633 /*
1634 * Same as the DT part.
1635 * Only support one UART on ARM which happen to be ns16550_com[0].
1636 */
1637 struct ns16550 *uart = &ns16550_com[0];
1638
1639 status = acpi_get_table(ACPI_SIG_SPCR, 0, &table);
1640 if ( ACPI_FAILURE(status) )
1641 {
1642 printk("ns16550: Failed to get SPCR table\n");
1643 return -EINVAL;
1644 }
1645
1646 spcr = container_of(table, struct acpi_table_spcr, header);
1647
1648 if ( unlikely(spcr->serial_port.space_id != ACPI_ADR_SPACE_SYSTEM_MEMORY) )
1649 {
1650 printk("ns16550: Address space type is not mmio\n");
1651 return -EINVAL;
1652 }
1653
1654 /*
1655 * The serial port address may be 0 for example
1656 * if the console redirection is disabled.
1657 */
1658 if ( unlikely(!spcr->serial_port.address) )
1659 {
1660 printk("ns16550: Console redirection is disabled\n");
1661 return -EINVAL;
1662 }
1663
1664 ns16550_init_common(uart);
1665
1666 /*
1667 * The baud rate is pre-configured by the firmware.
1668 * And currently the ACPI part is only targeting ARM so the flow_control
1669 * field and all PCI related ones which we do not care yet are ignored.
1670 */
1671 uart->baud = BAUD_AUTO;
1672 uart->data_bits = 8;
1673 uart->parity = spcr->parity;
1674 uart->stop_bits = spcr->stop_bits;
1675 uart->io_base = spcr->serial_port.address;
1676 uart->io_size = spcr->serial_port.bit_width;
1677 uart->reg_shift = spcr->serial_port.bit_offset;
1678 uart->reg_width = spcr->serial_port.access_width;
1679
1680 /* The trigger/polarity information is not available in spcr. */
1681 irq_set_type(spcr->interrupt, IRQ_TYPE_LEVEL_HIGH);
1682 uart->irq = spcr->interrupt;
1683
1684 uart->vuart.base_addr = uart->io_base;
1685 uart->vuart.size = uart->io_size;
1686 uart->vuart.data_off = UART_THR << uart->reg_shift;
1687 uart->vuart.status_off = UART_LSR << uart->reg_shift;
1688 uart->vuart.status = UART_LSR_THRE | UART_LSR_TEMT;
1689
1690 /* Register with generic serial driver. */
1691 serial_register_uart(SERHND_DTUART, &ns16550_driver, uart);
1692
1693 return 0;
1694 }
1695
1696 ACPI_DEVICE_START(ans16550, "NS16550 UART", DEVICE_SERIAL)
1697 .class_type = ACPI_DBG2_16550_COMPATIBLE,
1698 .init = ns16550_acpi_uart_init,
1699 ACPI_DEVICE_END
1700
1701 #endif /* CONFIG_ACPI && CONFIG_ARM */
1702
1703 /*
1704 * Local variables:
1705 * mode: C
1706 * c-file-style: "BSD"
1707 * c-basic-offset: 4
1708 * tab-width: 4
1709 * indent-tabs-mode: nil
1710 * End:
1711 */
1712