1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* 4 * This file contains definitions from Hyper-V Hypervisor Top-Level Functional 5 * Specification (TLFS): 6 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 7 */ 8 9 #ifndef _ASM_X86_HYPERV_TLFS_H 10 #define _ASM_X86_HYPERV_TLFS_H 11 12 #include <xen/bitops.h> 13 #include <xen/types.h> 14 #include <asm/page.h> 15 16 /* 17 * While not explicitly listed in the TLFS, Hyper-V always runs with a page size 18 * of 4096. These definitions are used when communicating with Hyper-V using 19 * guest physical pages and guest physical page addresses, since the guest page 20 * size may not be 4096 on all architectures. 21 */ 22 #define HV_HYP_PAGE_SHIFT 12 23 #define HV_HYP_PAGE_SIZE BIT(HV_HYP_PAGE_SHIFT, UL) 24 #define HV_HYP_PAGE_MASK (~(HV_HYP_PAGE_SIZE - 1)) 25 26 /* 27 * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent 28 * is set by CPUID(HvCpuIdFunctionVersionAndFeatures). 29 */ 30 #define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000 31 #define HYPERV_CPUID_INTERFACE 0x40000001 32 #define HYPERV_CPUID_VERSION 0x40000002 33 #define HYPERV_CPUID_FEATURES 0x40000003 34 #define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004 35 #define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005 36 #define HYPERV_CPUID_NESTED_FEATURES 0x4000000A 37 38 #define HYPERV_HYPERVISOR_PRESENT_BIT 0x80000000 39 #define HYPERV_CPUID_MIN 0x40000005 40 #define HYPERV_CPUID_MAX 0x4000ffff 41 42 /* 43 * Feature identification. EAX indicates which features are available 44 * to the partition based upon the current partition privileges. 45 * These are HYPERV_CPUID_FEATURES.EAX bits. 46 */ 47 48 /* VP Runtime (HV_X64_MSR_VP_RUNTIME) available */ 49 #define HV_X64_MSR_VP_RUNTIME_AVAILABLE BIT(0, UL) 50 /* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/ 51 #define HV_MSR_TIME_REF_COUNT_AVAILABLE BIT(1, UL) 52 /* 53 * Basic SynIC MSRs (HV_X64_MSR_SCONTROL through HV_X64_MSR_EOM 54 * and HV_X64_MSR_SINT0 through HV_X64_MSR_SINT15) available 55 */ 56 #define HV_X64_MSR_SYNIC_AVAILABLE BIT(2, UL) 57 /* 58 * Synthetic Timer MSRs (HV_X64_MSR_STIMER0_CONFIG through 59 * HV_X64_MSR_STIMER3_COUNT) available 60 */ 61 #define HV_MSR_SYNTIMER_AVAILABLE BIT(3, UL) 62 /* 63 * APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR) 64 * are available 65 */ 66 #define HV_X64_MSR_APIC_ACCESS_AVAILABLE BIT(4, UL) 67 /* Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) available*/ 68 #define HV_X64_MSR_HYPERCALL_AVAILABLE BIT(5, UL) 69 /* Access virtual processor index MSR (HV_X64_MSR_VP_INDEX) available*/ 70 #define HV_X64_MSR_VP_INDEX_AVAILABLE BIT(6, UL) 71 /* Virtual system reset MSR (HV_X64_MSR_RESET) is available*/ 72 #define HV_X64_MSR_RESET_AVAILABLE BIT(7, UL) 73 /* 74 * Access statistics pages MSRs (HV_X64_MSR_STATS_PARTITION_RETAIL_PAGE, 75 * HV_X64_MSR_STATS_PARTITION_INTERNAL_PAGE, HV_X64_MSR_STATS_VP_RETAIL_PAGE, 76 * HV_X64_MSR_STATS_VP_INTERNAL_PAGE) available 77 */ 78 #define HV_X64_MSR_STAT_PAGES_AVAILABLE BIT(8, UL) 79 /* Partition reference TSC MSR is available */ 80 #define HV_MSR_REFERENCE_TSC_AVAILABLE BIT(9, UL) 81 /* Partition Guest IDLE MSR is available */ 82 #define HV_X64_MSR_GUEST_IDLE_AVAILABLE BIT(10, UL) 83 /* 84 * There is a single feature flag that signifies if the partition has access 85 * to MSRs with local APIC and TSC frequencies. 86 */ 87 #define HV_X64_ACCESS_FREQUENCY_MSRS BIT(11, UL) 88 /* AccessReenlightenmentControls privilege */ 89 #define HV_X64_ACCESS_REENLIGHTENMENT BIT(13, UL) 90 91 /* 92 * Feature identification: indicates which flags were specified at partition 93 * creation. The format is the same as the partition creation flag structure 94 * defined in section Partition Creation Flags. 95 * These are HYPERV_CPUID_FEATURES.EBX bits. 96 */ 97 #define HV_X64_CREATE_PARTITIONS BIT(0, UL) 98 #define HV_X64_ACCESS_PARTITION_ID BIT(1, UL) 99 #define HV_X64_ACCESS_MEMORY_POOL BIT(2, UL) 100 #define HV_X64_ADJUST_MESSAGE_BUFFERS BIT(3, UL) 101 #define HV_X64_POST_MESSAGES BIT(4, UL) 102 #define HV_X64_SIGNAL_EVENTS BIT(5, UL) 103 #define HV_X64_CREATE_PORT BIT(6, UL) 104 #define HV_X64_CONNECT_PORT BIT(7, UL) 105 #define HV_X64_ACCESS_STATS BIT(8, UL) 106 #define HV_X64_DEBUGGING BIT(11, UL) 107 #define HV_X64_CPU_POWER_MANAGEMENT BIT(12, UL) 108 109 /* 110 * Feature identification. EDX indicates which miscellaneous features 111 * are available to the partition. 112 * These are HYPERV_CPUID_FEATURES.EDX bits. 113 */ 114 /* The MWAIT instruction is available (per section MONITOR / MWAIT) */ 115 #define HV_X64_MWAIT_AVAILABLE BIT(0, UL) 116 /* Guest debugging support is available */ 117 #define HV_X64_GUEST_DEBUGGING_AVAILABLE BIT(1, UL) 118 /* Performance Monitor support is available*/ 119 #define HV_X64_PERF_MONITOR_AVAILABLE BIT(2, UL) 120 /* Support for physical CPU dynamic partitioning events is available*/ 121 #define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE BIT(3, UL) 122 /* 123 * Support for passing hypercall input parameter block via XMM 124 * registers is available 125 */ 126 #define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE BIT(4, UL) 127 /* Support for a virtual guest idle state is available */ 128 #define HV_X64_GUEST_IDLE_STATE_AVAILABLE BIT(5, UL) 129 /* Frequency MSRs available */ 130 #define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE BIT(8, UL) 131 /* Crash MSR available */ 132 #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE BIT(10, UL) 133 /* stimer Direct Mode is available */ 134 #define HV_STIMER_DIRECT_MODE_AVAILABLE BIT(19, UL) 135 136 /* 137 * Implementation recommendations. Indicates which behaviors the hypervisor 138 * recommends the OS implement for optimal performance. 139 * These are HYPERV_CPUID_ENLIGHTMENT_INFO.EAX bits. 140 */ 141 /* 142 * Recommend using hypercall for address space switches rather 143 * than MOV to CR3 instruction 144 */ 145 #define HV_X64_AS_SWITCH_RECOMMENDED BIT(0, UL) 146 /* Recommend using hypercall for local TLB flushes rather 147 * than INVLPG or MOV to CR3 instructions */ 148 #define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED BIT(1, UL) 149 /* 150 * Recommend using hypercall for remote TLB flushes rather 151 * than inter-processor interrupts 152 */ 153 #define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED BIT(2, UL) 154 /* 155 * Recommend using MSRs for accessing APIC registers 156 * EOI, ICR and TPR rather than their memory-mapped counterparts 157 */ 158 #define HV_X64_APIC_ACCESS_RECOMMENDED BIT(3, UL) 159 /* Recommend using the hypervisor-provided MSR to initiate a system RESET */ 160 #define HV_X64_SYSTEM_RESET_RECOMMENDED BIT(4, UL) 161 /* 162 * Recommend using relaxed timing for this partition. If used, 163 * the VM should disable any watchdog timeouts that rely on the 164 * timely delivery of external interrupts 165 */ 166 #define HV_X64_RELAXED_TIMING_RECOMMENDED BIT(5, UL) 167 168 /* 169 * Recommend not using Auto End-Of-Interrupt feature 170 */ 171 #define HV_DEPRECATING_AEOI_RECOMMENDED BIT(9, UL) 172 173 /* 174 * Recommend using cluster IPI hypercalls. 175 */ 176 #define HV_X64_CLUSTER_IPI_RECOMMENDED BIT(10, UL) 177 178 /* Recommend using the newer ExProcessorMasks interface */ 179 #define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED BIT(11, UL) 180 181 /* Recommend using enlightened VMCS */ 182 #define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED BIT(14, UL) 183 184 /* 185 * Virtual processor will never share a physical core with another virtual 186 * processor, except for virtual processors that are reported as sibling SMT 187 * threads. 188 */ 189 #define HV_X64_NO_NONARCH_CORESHARING BIT(18, UL) 190 191 /* Nested features. These are HYPERV_CPUID_NESTED_FEATURES.EAX bits. */ 192 #define HV_X64_NESTED_DIRECT_FLUSH BIT(17, UL) 193 #define HV_X64_NESTED_GUEST_MAPPING_FLUSH BIT(18, UL) 194 #define HV_X64_NESTED_MSR_BITMAP BIT(19, UL) 195 196 /* Hyper-V specific model specific registers (MSRs) */ 197 198 /* MSR used to identify the guest OS. */ 199 #define HV_X64_MSR_GUEST_OS_ID 0x40000000 200 201 /* MSR used to setup pages used to communicate with the hypervisor. */ 202 #define HV_X64_MSR_HYPERCALL 0x40000001 203 204 /* MSR used to provide vcpu index */ 205 #define HV_X64_MSR_VP_INDEX 0x40000002 206 207 /* MSR used to reset the guest OS. */ 208 #define HV_X64_MSR_RESET 0x40000003 209 210 /* MSR used to provide vcpu runtime in 100ns units */ 211 #define HV_X64_MSR_VP_RUNTIME 0x40000010 212 213 /* MSR used to read the per-partition time reference counter */ 214 #define HV_X64_MSR_TIME_REF_COUNT 0x40000020 215 216 /* A partition's reference time stamp counter (TSC) page */ 217 #define HV_X64_MSR_REFERENCE_TSC 0x40000021 218 219 /* MSR used to retrieve the TSC frequency */ 220 #define HV_X64_MSR_TSC_FREQUENCY 0x40000022 221 222 /* MSR used to retrieve the local APIC timer frequency */ 223 #define HV_X64_MSR_APIC_FREQUENCY 0x40000023 224 225 /* Define the virtual APIC registers */ 226 #define HV_X64_MSR_EOI 0x40000070 227 #define HV_X64_MSR_ICR 0x40000071 228 #define HV_X64_MSR_TPR 0x40000072 229 #define HV_X64_MSR_VP_ASSIST_PAGE 0x40000073 230 231 /* Define synthetic interrupt controller model specific registers. */ 232 #define HV_X64_MSR_SCONTROL 0x40000080 233 #define HV_X64_MSR_SVERSION 0x40000081 234 #define HV_X64_MSR_SIEFP 0x40000082 235 #define HV_X64_MSR_SIMP 0x40000083 236 #define HV_X64_MSR_EOM 0x40000084 237 #define HV_X64_MSR_SINT0 0x40000090 238 #define HV_X64_MSR_SINT1 0x40000091 239 #define HV_X64_MSR_SINT2 0x40000092 240 #define HV_X64_MSR_SINT3 0x40000093 241 #define HV_X64_MSR_SINT4 0x40000094 242 #define HV_X64_MSR_SINT5 0x40000095 243 #define HV_X64_MSR_SINT6 0x40000096 244 #define HV_X64_MSR_SINT7 0x40000097 245 #define HV_X64_MSR_SINT8 0x40000098 246 #define HV_X64_MSR_SINT9 0x40000099 247 #define HV_X64_MSR_SINT10 0x4000009A 248 #define HV_X64_MSR_SINT11 0x4000009B 249 #define HV_X64_MSR_SINT12 0x4000009C 250 #define HV_X64_MSR_SINT13 0x4000009D 251 #define HV_X64_MSR_SINT14 0x4000009E 252 #define HV_X64_MSR_SINT15 0x4000009F 253 254 /* 255 * Synthetic Timer MSRs. Four timers per vcpu. 256 */ 257 #define HV_X64_MSR_STIMER0_CONFIG 0x400000B0 258 #define HV_X64_MSR_STIMER0_COUNT 0x400000B1 259 #define HV_X64_MSR_STIMER1_CONFIG 0x400000B2 260 #define HV_X64_MSR_STIMER1_COUNT 0x400000B3 261 #define HV_X64_MSR_STIMER2_CONFIG 0x400000B4 262 #define HV_X64_MSR_STIMER2_COUNT 0x400000B5 263 #define HV_X64_MSR_STIMER3_CONFIG 0x400000B6 264 #define HV_X64_MSR_STIMER3_COUNT 0x400000B7 265 266 /* Hyper-V guest idle MSR */ 267 #define HV_X64_MSR_GUEST_IDLE 0x400000F0 268 269 /* Hyper-V guest crash notification MSR's */ 270 #define HV_X64_MSR_CRASH_P0 0x40000100 271 #define HV_X64_MSR_CRASH_P1 0x40000101 272 #define HV_X64_MSR_CRASH_P2 0x40000102 273 #define HV_X64_MSR_CRASH_P3 0x40000103 274 #define HV_X64_MSR_CRASH_P4 0x40000104 275 #define HV_X64_MSR_CRASH_CTL 0x40000105 276 277 /* TSC emulation after migration */ 278 #define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106 279 #define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107 280 #define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108 281 282 /* 283 * Declare the MSR used to setup pages used to communicate with the hypervisor. 284 */ 285 union hv_x64_msr_hypercall_contents { 286 u64 as_uint64; 287 struct { 288 u64 enable:1; 289 u64 reserved:11; 290 u64 guest_physical_address:52; 291 }; 292 }; 293 294 /* 295 * TSC page layout. 296 */ 297 struct ms_hyperv_tsc_page { 298 volatile u32 tsc_sequence; 299 u32 reserved1; 300 volatile u64 tsc_scale; 301 volatile s64 tsc_offset; 302 u64 reserved2[509]; 303 }; 304 305 /* 306 * The guest OS needs to register the guest ID with the hypervisor. 307 * The guest ID is a 64 bit entity and the structure of this ID is 308 * specified in the Hyper-V specification: 309 * 310 * msdn.microsoft.com/en-us/library/windows/hardware/ff542653%28v=vs.85%29.aspx 311 * 312 * While the current guideline does not specify how Linux guest ID(s) 313 * need to be generated, our plan is to publish the guidelines for 314 * Linux and other guest operating systems that currently are hosted 315 * on Hyper-V. The implementation here conforms to this yet 316 * unpublished guidelines. 317 * 318 * 319 * Bit(s) 320 * 63 - Indicates if the OS is Open Source or not; 1 is Open Source 321 * 62:56 - Os Type; Linux 0x1, FreeBSD 0x2, Xen 0x3 322 * 55:48 - Distro specific identification 323 * 47:16 - Guest OS version number 324 * 15:0 - Distro specific identification 325 * 326 * 327 */ 328 329 #define HV_LINUX_VENDOR_ID 0x8100 330 #define HV_XEN_VENDOR_ID 0x8300 331 union hv_guest_os_id 332 { 333 uint64_t raw; 334 struct 335 { 336 uint64_t build_number:16; 337 uint64_t service_pack:8; 338 uint64_t minor:8; 339 uint64_t major:8; 340 uint64_t os:8; 341 uint64_t vendor:16; 342 }; 343 }; 344 345 struct hv_reenlightenment_control { 346 __u64 vector:8; 347 __u64 reserved1:8; 348 __u64 enabled:1; 349 __u64 reserved2:15; 350 __u64 target_vp:32; 351 }; 352 353 struct hv_tsc_emulation_control { 354 __u64 enabled:1; 355 __u64 reserved:63; 356 }; 357 358 struct hv_tsc_emulation_status { 359 __u64 inprogress:1; 360 __u64 reserved:63; 361 }; 362 363 #define HV_X64_MSR_HYPERCALL_ENABLE 0x00000001 364 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12 365 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \ 366 (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1)) 367 368 /* 369 * Crash notification (HV_X64_MSR_CRASH_CTL) flags. 370 */ 371 #define HV_CRASH_CTL_CRASH_NOTIFY_MSG BIT_ULL(62) 372 #define HV_CRASH_CTL_CRASH_NOTIFY BIT_ULL(63) 373 #define HV_X64_MSR_CRASH_PARAMS \ 374 (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0)) 375 376 #define HV_IPI_LOW_VECTOR 0x10 377 #define HV_IPI_HIGH_VECTOR 0xff 378 379 /* Declare the various hypercall operations. */ 380 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE 0x0002 381 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST 0x0003 382 #define HVCALL_NOTIFY_LONG_SPIN_WAIT 0x0008 383 #define HVCALL_SEND_IPI 0x000b 384 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX 0x0013 385 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST_EX 0x0014 386 #define HVCALL_SEND_IPI_EX 0x0015 387 #define HVCALL_POST_MESSAGE 0x005c 388 #define HVCALL_SIGNAL_EVENT 0x005d 389 #define HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE 0x00af 390 #define HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_LIST 0x00b0 391 #define HVCALL_EXT_CALL_QUERY_CAPABILITIES 0x8001 392 393 #define HV_X64_MSR_VP_ASSIST_PAGE_ENABLE 0x00000001 394 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT 12 395 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK \ 396 (~((1ull << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT) - 1)) 397 398 /* Hyper-V Enlightened VMCS version mask in nested features CPUID */ 399 #define HV_X64_ENLIGHTENED_VMCS_VERSION 0xff 400 401 #define HV_X64_MSR_TSC_REFERENCE_ENABLE 0x00000001 402 #define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT 12 403 404 #define HV_PROCESSOR_POWER_STATE_C0 0 405 #define HV_PROCESSOR_POWER_STATE_C1 1 406 #define HV_PROCESSOR_POWER_STATE_C2 2 407 #define HV_PROCESSOR_POWER_STATE_C3 3 408 409 #define HV_FLUSH_ALL_PROCESSORS BIT(0, UL) 410 #define HV_FLUSH_ALL_VIRTUAL_ADDRESS_SPACES BIT(1, UL) 411 #define HV_FLUSH_NON_GLOBAL_MAPPINGS_ONLY BIT(2, UL) 412 #define HV_FLUSH_USE_EXTENDED_RANGE_FORMAT BIT(3, UL) 413 414 enum HV_GENERIC_SET_FORMAT { 415 HV_GENERIC_SET_SPARSE_4K, 416 HV_GENERIC_SET_ALL, 417 }; 418 419 #define HV_HYPERCALL_RESULT_MASK 0xffff /* GENMASK_ULL(15, 0) */ 420 #define HV_HYPERCALL_FAST_BIT BIT(16, UL) 421 #define HV_HYPERCALL_VARHEAD_OFFSET 17 422 #define HV_HYPERCALL_REP_COMP_OFFSET 32 423 #define HV_HYPERCALL_REP_COMP_MASK (0xfffULL << HV_HYPERCALL_REP_COMP_OFFSET) /* GENMASK_ULL(43, 32) */ 424 #define HV_HYPERCALL_REP_START_OFFSET 48 425 #define HV_HYPERCALL_REP_START_MASK (0xfffULL << HV_HYPERCALL_REP_START_OFFSET) /* GENMASK_ULL(59, 48) */ 426 427 /* hypercall status code */ 428 #define HV_STATUS_SUCCESS 0 429 #define HV_STATUS_INVALID_HYPERCALL_CODE 2 430 #define HV_STATUS_INVALID_HYPERCALL_INPUT 3 431 #define HV_STATUS_INVALID_ALIGNMENT 4 432 #define HV_STATUS_INVALID_PARAMETER 5 433 #define HV_STATUS_INSUFFICIENT_MEMORY 11 434 #define HV_STATUS_INVALID_PORT_ID 17 435 #define HV_STATUS_INVALID_CONNECTION_ID 18 436 #define HV_STATUS_INSUFFICIENT_BUFFERS 19 437 438 /* 439 * The Hyper-V TimeRefCount register and the TSC 440 * page provide a guest VM clock with 100ns tick rate 441 */ 442 #define HV_CLOCK_HZ (NSEC_PER_SEC/100) 443 444 typedef struct _HV_REFERENCE_TSC_PAGE { 445 __u32 tsc_sequence; 446 __u32 res1; 447 __u64 tsc_scale; 448 __s64 tsc_offset; 449 } HV_REFERENCE_TSC_PAGE, *PHV_REFERENCE_TSC_PAGE; 450 451 /* Define the number of synthetic interrupt sources. */ 452 #define HV_SYNIC_SINT_COUNT (16) 453 /* Define the expected SynIC version. */ 454 #define HV_SYNIC_VERSION_1 (0x1) 455 /* Valid SynIC vectors are 16-255. */ 456 #define HV_SYNIC_FIRST_VALID_VECTOR (16) 457 458 #define HV_SYNIC_CONTROL_ENABLE (1ULL << 0) 459 #define HV_SYNIC_SIMP_ENABLE (1ULL << 0) 460 #define HV_SYNIC_SIEFP_ENABLE (1ULL << 0) 461 #define HV_SYNIC_SINT_MASKED (1ULL << 16) 462 #define HV_SYNIC_SINT_AUTO_EOI (1ULL << 17) 463 #define HV_SYNIC_SINT_VECTOR_MASK (0xFF) 464 465 #define HV_SYNIC_STIMER_COUNT (4) 466 467 /* Define synthetic interrupt controller message constants. */ 468 #define HV_MESSAGE_SIZE (256) 469 #define HV_MESSAGE_PAYLOAD_BYTE_COUNT (240) 470 #define HV_MESSAGE_PAYLOAD_QWORD_COUNT (30) 471 472 /* Define hypervisor message types. */ 473 enum hv_message_type { 474 HVMSG_NONE = 0x00000000, 475 476 /* Memory access messages. */ 477 HVMSG_UNMAPPED_GPA = 0x80000000, 478 HVMSG_GPA_INTERCEPT = 0x80000001, 479 480 /* Timer notification messages. */ 481 HVMSG_TIMER_EXPIRED = 0x80000010, 482 483 /* Error messages. */ 484 HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020, 485 HVMSG_UNRECOVERABLE_EXCEPTION = 0x80000021, 486 HVMSG_UNSUPPORTED_FEATURE = 0x80000022, 487 488 /* Trace buffer complete messages. */ 489 HVMSG_EVENTLOG_BUFFERCOMPLETE = 0x80000040, 490 491 /* Platform-specific processor intercept messages. */ 492 HVMSG_X64_IOPORT_INTERCEPT = 0x80010000, 493 HVMSG_X64_MSR_INTERCEPT = 0x80010001, 494 HVMSG_X64_CPUID_INTERCEPT = 0x80010002, 495 HVMSG_X64_EXCEPTION_INTERCEPT = 0x80010003, 496 HVMSG_X64_APIC_EOI = 0x80010004, 497 HVMSG_X64_LEGACY_FP_ERROR = 0x80010005 498 }; 499 500 /* Define synthetic interrupt controller message flags. */ 501 union hv_message_flags { 502 __u8 asu8; 503 struct { 504 __u8 msg_pending:1; 505 __u8 reserved:7; 506 }; 507 }; 508 509 /* Define port identifier type. */ 510 union hv_port_id { 511 __u32 asu32; 512 struct { 513 __u32 id:24; 514 __u32 reserved:8; 515 } u; 516 }; 517 518 /* Define synthetic interrupt controller message header. */ 519 struct hv_message_header { 520 __u32 message_type; 521 __u8 payload_size; 522 union hv_message_flags message_flags; 523 __u8 reserved[2]; 524 union { 525 __u64 sender; 526 union hv_port_id port; 527 }; 528 }; 529 530 /* Define synthetic interrupt controller message format. */ 531 struct hv_message { 532 struct hv_message_header header; 533 union { 534 __u64 payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT]; 535 } u; 536 }; 537 538 /* Define the synthetic interrupt message page layout. */ 539 struct hv_message_page { 540 struct hv_message sint_message[HV_SYNIC_SINT_COUNT]; 541 }; 542 543 /* Define timer message payload structure. */ 544 struct hv_timer_message_payload { 545 __u32 timer_index; 546 __u32 reserved; 547 __u64 expiration_time; /* When the timer expired */ 548 __u64 delivery_time; /* When the message was delivered */ 549 }; 550 551 struct hv_nested_enlightenments_control { 552 struct { 553 __u32 directhypercall:1; 554 __u32 reserved:31; 555 } features; 556 struct { 557 __u32 reserved; 558 } hypercallControls; 559 }; 560 561 union hv_vp_assist_page_msr 562 { 563 uint64_t raw; 564 struct 565 { 566 uint64_t enabled:1; 567 uint64_t reserved_preserved:11; 568 uint64_t pfn:48; 569 }; 570 }; 571 572 /* Define virtual processor assist page structure. */ 573 struct hv_vp_assist_page { 574 __u32 apic_assist; 575 __u32 reserved1; 576 __u64 vtl_control[3]; 577 struct hv_nested_enlightenments_control nested_control; 578 __u8 enlighten_vmentry; 579 __u8 reserved2[7]; 580 __u64 current_nested_vmcs; 581 }; 582 583 struct hv_enlightened_vmcs { 584 u32 revision_id; 585 u32 abort; 586 587 u16 host_es_selector; 588 u16 host_cs_selector; 589 u16 host_ss_selector; 590 u16 host_ds_selector; 591 u16 host_fs_selector; 592 u16 host_gs_selector; 593 u16 host_tr_selector; 594 595 u16 padding16_1; 596 597 u64 host_ia32_pat; 598 u64 host_ia32_efer; 599 600 u64 host_cr0; 601 u64 host_cr3; 602 u64 host_cr4; 603 604 u64 host_ia32_sysenter_esp; 605 u64 host_ia32_sysenter_eip; 606 u64 host_rip; 607 u32 host_ia32_sysenter_cs; 608 609 u32 pin_based_vm_exec_control; 610 u32 vm_exit_controls; 611 u32 secondary_vm_exec_control; 612 613 u64 io_bitmap_a; 614 u64 io_bitmap_b; 615 u64 msr_bitmap; 616 617 u16 guest_es_selector; 618 u16 guest_cs_selector; 619 u16 guest_ss_selector; 620 u16 guest_ds_selector; 621 u16 guest_fs_selector; 622 u16 guest_gs_selector; 623 u16 guest_ldtr_selector; 624 u16 guest_tr_selector; 625 626 u32 guest_es_limit; 627 u32 guest_cs_limit; 628 u32 guest_ss_limit; 629 u32 guest_ds_limit; 630 u32 guest_fs_limit; 631 u32 guest_gs_limit; 632 u32 guest_ldtr_limit; 633 u32 guest_tr_limit; 634 u32 guest_gdtr_limit; 635 u32 guest_idtr_limit; 636 637 u32 guest_es_ar_bytes; 638 u32 guest_cs_ar_bytes; 639 u32 guest_ss_ar_bytes; 640 u32 guest_ds_ar_bytes; 641 u32 guest_fs_ar_bytes; 642 u32 guest_gs_ar_bytes; 643 u32 guest_ldtr_ar_bytes; 644 u32 guest_tr_ar_bytes; 645 646 u64 guest_es_base; 647 u64 guest_cs_base; 648 u64 guest_ss_base; 649 u64 guest_ds_base; 650 u64 guest_fs_base; 651 u64 guest_gs_base; 652 u64 guest_ldtr_base; 653 u64 guest_tr_base; 654 u64 guest_gdtr_base; 655 u64 guest_idtr_base; 656 657 u64 padding64_1[3]; 658 659 u64 vm_exit_msr_store_addr; 660 u64 vm_exit_msr_load_addr; 661 u64 vm_entry_msr_load_addr; 662 663 u64 cr3_target_value0; 664 u64 cr3_target_value1; 665 u64 cr3_target_value2; 666 u64 cr3_target_value3; 667 668 u32 page_fault_error_code_mask; 669 u32 page_fault_error_code_match; 670 671 u32 cr3_target_count; 672 u32 vm_exit_msr_store_count; 673 u32 vm_exit_msr_load_count; 674 u32 vm_entry_msr_load_count; 675 676 u64 tsc_offset; 677 u64 virtual_apic_page_addr; 678 u64 vmcs_link_pointer; 679 680 u64 guest_ia32_debugctl; 681 u64 guest_ia32_pat; 682 u64 guest_ia32_efer; 683 684 u64 guest_pdptr0; 685 u64 guest_pdptr1; 686 u64 guest_pdptr2; 687 u64 guest_pdptr3; 688 689 u64 guest_pending_dbg_exceptions; 690 u64 guest_sysenter_esp; 691 u64 guest_sysenter_eip; 692 693 u32 guest_activity_state; 694 u32 guest_sysenter_cs; 695 696 u64 cr0_guest_host_mask; 697 u64 cr4_guest_host_mask; 698 u64 cr0_read_shadow; 699 u64 cr4_read_shadow; 700 u64 guest_cr0; 701 u64 guest_cr3; 702 u64 guest_cr4; 703 u64 guest_dr7; 704 705 u64 host_fs_base; 706 u64 host_gs_base; 707 u64 host_tr_base; 708 u64 host_gdtr_base; 709 u64 host_idtr_base; 710 u64 host_rsp; 711 712 u64 ept_pointer; 713 714 u16 virtual_processor_id; 715 u16 padding16_2[3]; 716 717 u64 padding64_2[5]; 718 u64 guest_physical_address; 719 720 u32 vm_instruction_error; 721 u32 vm_exit_reason; 722 u32 vm_exit_intr_info; 723 u32 vm_exit_intr_error_code; 724 u32 idt_vectoring_info_field; 725 u32 idt_vectoring_error_code; 726 u32 vm_exit_instruction_len; 727 u32 vmx_instruction_info; 728 729 u64 exit_qualification; 730 u64 exit_io_instruction_ecx; 731 u64 exit_io_instruction_esi; 732 u64 exit_io_instruction_edi; 733 u64 exit_io_instruction_eip; 734 735 u64 guest_linear_address; 736 u64 guest_rsp; 737 u64 guest_rflags; 738 739 u32 guest_interruptibility_info; 740 u32 cpu_based_vm_exec_control; 741 u32 exception_bitmap; 742 u32 vm_entry_controls; 743 u32 vm_entry_intr_info_field; 744 u32 vm_entry_exception_error_code; 745 u32 vm_entry_instruction_len; 746 u32 tpr_threshold; 747 748 u64 guest_rip; 749 750 u32 hv_clean_fields; 751 u32 hv_padding_32; 752 u32 hv_synthetic_controls; 753 struct { 754 u32 nested_flush_hypercall:1; 755 u32 msr_bitmap:1; 756 u32 reserved:30; 757 } hv_enlightenments_control; 758 u32 hv_vp_id; 759 760 u64 hv_vm_id; 761 u64 partition_assist_page; 762 u64 padding64_4[4]; 763 u64 guest_bndcfgs; 764 u64 padding64_5[7]; 765 u64 xss_exit_bitmap; 766 u64 padding64_6[7]; 767 }; 768 769 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_NONE 0 770 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_IO_BITMAP BIT(0, UL) 771 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP BIT(1, UL) 772 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP2 BIT(2, UL) 773 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP1 BIT(3, UL) 774 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC BIT(4, UL) 775 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EVENT BIT(5, UL) 776 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_ENTRY BIT(6, UL) 777 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EXCPN BIT(7, UL) 778 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CRDR BIT(8, UL) 779 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_XLAT BIT(9, UL) 780 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_BASIC BIT(10, UL) 781 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1 BIT(11, UL) 782 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2 BIT(12, UL) 783 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_POINTER BIT(13, UL) 784 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1 BIT(14, UL) 785 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ENLIGHTENMENTSCONTROL BIT(15, UL) 786 787 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL 0xFFFF 788 789 /* Define synthetic interrupt controller flag constants. */ 790 #define HV_EVENT_FLAGS_COUNT (256 * 8) 791 #define HV_EVENT_FLAGS_LONG_COUNT (256 / sizeof(unsigned long)) 792 793 /* 794 * Synthetic timer configuration. 795 */ 796 union hv_stimer_config { 797 u64 as_uint64; 798 struct { 799 u64 enable:1; 800 u64 periodic:1; 801 u64 lazy:1; 802 u64 auto_enable:1; 803 u64 apic_vector:8; 804 u64 direct_mode:1; 805 u64 reserved_z0:3; 806 u64 sintx:4; 807 u64 reserved_z1:44; 808 }; 809 }; 810 811 812 /* Define the synthetic interrupt controller event flags format. */ 813 union hv_synic_event_flags { 814 unsigned long flags[HV_EVENT_FLAGS_LONG_COUNT]; 815 }; 816 817 /* Define SynIC control register. */ 818 union hv_synic_scontrol { 819 u64 as_uint64; 820 struct { 821 u64 enable:1; 822 u64 reserved:63; 823 }; 824 }; 825 826 /* Define synthetic interrupt source. */ 827 union hv_synic_sint { 828 u64 as_uint64; 829 struct { 830 u64 vector:8; 831 u64 reserved1:8; 832 u64 masked:1; 833 u64 auto_eoi:1; 834 u64 polling:1; 835 u64 reserved2:45; 836 }; 837 }; 838 839 /* Define the format of the SIMP register */ 840 union hv_synic_simp { 841 u64 as_uint64; 842 struct { 843 u64 simp_enabled:1; 844 u64 preserved:11; 845 u64 base_simp_gpa:52; 846 }; 847 }; 848 849 /* Define the format of the SIEFP register */ 850 union hv_synic_siefp { 851 u64 as_uint64; 852 struct { 853 u64 siefp_enabled:1; 854 u64 preserved:11; 855 u64 base_siefp_gpa:52; 856 }; 857 }; 858 859 struct hv_vpset { 860 u64 format; 861 u64 valid_bank_mask; 862 u64 bank_contents[]; 863 }; 864 865 /* HvCallSendSyntheticClusterIpi hypercall */ 866 struct hv_send_ipi { 867 u32 vector; 868 u32 reserved; 869 u64 cpu_mask; 870 }; 871 872 /* HvCallSendSyntheticClusterIpiEx hypercall */ 873 struct hv_send_ipi_ex { 874 u32 vector; 875 u32 reserved; 876 struct hv_vpset vp_set; 877 }; 878 879 /* HvFlushGuestPhysicalAddressSpace hypercalls */ 880 struct hv_guest_mapping_flush { 881 u64 address_space; 882 u64 flags; 883 }; 884 885 /* 886 * HV_MAX_FLUSH_PAGES = "additional_pages" + 1. It's limited 887 * by the bitwidth of "additional_pages" in union hv_gpa_page_range. 888 */ 889 #define HV_MAX_FLUSH_PAGES (2048) 890 891 /* HvFlushGuestPhysicalAddressList hypercall */ 892 union hv_gpa_page_range { 893 u64 address_space; 894 struct { 895 u64 additional_pages:11; 896 u64 largepage:1; 897 u64 basepfn:52; 898 } page; 899 }; 900 901 /* 902 * All input flush parameters should be in single page. The max flush 903 * count is equal with how many entries of union hv_gpa_page_range can 904 * be populated into the input parameter page. 905 */ 906 #define HV_MAX_FLUSH_REP_COUNT ((HV_HYP_PAGE_SIZE - 2 * sizeof(u64)) / \ 907 sizeof(union hv_gpa_page_range)) 908 909 struct hv_guest_mapping_flush_list { 910 u64 address_space; 911 u64 flags; 912 union hv_gpa_page_range gpa_list[HV_MAX_FLUSH_REP_COUNT]; 913 }; 914 915 /* HvFlushVirtualAddressSpace, HvFlushVirtualAddressList hypercalls */ 916 struct hv_tlb_flush { 917 u64 address_space; 918 u64 flags; 919 u64 processor_mask; 920 u64 gva_list[]; 921 }; 922 923 /* HvFlushVirtualAddressSpaceEx hypercall */ 924 struct hv_tlb_flush_ex { 925 u64 address_space; 926 u64 flags; 927 struct hv_vpset hv_vp_set; 928 /* u64 gva_list[]; */ 929 }; 930 931 struct hv_partition_assist_pg { 932 u32 tlb_lock_count; 933 }; 934 #endif 935