MPAMF_OUT_TL_IDR, MPAM Egress PARTID Translation ID Register

The MPAMF_OUT_TL_IDR characteristics are:

Purpose

Indicates the egress PARTID translation capabilities of the MSC.

Configuration

The power domain of MPAMF_OUT_TL_IDR is IMPLEMENTATION DEFINED.

This register is present only when FEAT_MPAM_MSC_DOMAINS is implemented and MPAMF_IDR.HAS_OUT_TL == 1. Otherwise, direct accesses to MPAMF_OUT_TL_IDR are RES0.

The power and reset domain of each MSC component is specific to that component.

Attributes

MPAMF_OUT_TL_IDR is a 32-bit register.

Field descriptions

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
HAS_DIRECT_TL	HAS_BASE_MASK	RES0														OUT_PARTID_MAX

HAS_DIRECT_TL, bit [31]

Indicates support for direct egress translation of PARTIDs.

The value of this field is an IMPLEMENTATION DEFINED choice of:

HAS_DIRECT_TL	Meaning
0b0	Direct egress translation of PARTIDs is not supported.
0b1	Direct egress translation of PARTIDs is supported for those PARTIDs with an explicitly set translation configuration.

Access to this field is RO.

HAS_BASE_MASK, bit [30]

Indicates support for computed egress translation of PARTIDs using a configurable mask and base.

The value of this field is an IMPLEMENTATION DEFINED choice of:

HAS_BASE_MASK	Meaning
0b0	Computed egress translation of PARTIDs using a configurable mask and base is not supported.
0b1	Computed egress translation of PARTIDs using a configurable mask and base is supported for those PARTIDs without an explicitly set translation configuration.

Access to this field is RO.

Bits [29:16]

Reserved, RES0.

OUT_PARTID_MAX, bits [15:0]
When MPAMF_OUT_TL_IDR.HAS_DIRECT_TL == 1:

Maximum value for PARTIDs to be used as direct egress translations, as configured in MPAMCFG_OUT_TL.PARTID_TL.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

Otherwise:

Reserved, RES0.

Accessing MPAMF_OUT_TL_IDR

This register is within the MPAM feature page memory frames. In a system that supports Secure, Non-secure, Root, and Realm memory maps, there must be MPAM feature pages in all four address maps.

MPAMF_OUT_TL_IDR is read-only.

MPAMF_OUT_TL_IDR must be readable from the Non-secure, Secure, Root, and Realm MPAM feature pages.

MPAMF_OUT_TL_IDR is permitted to have the same contents when read from the Secure, Non-secure, Root, and Realm MPAM feature pages unless the register contents are different for the different versions:

MPAMF_OUT_TL_IDR_s is permitted to have either the same or different contents to MPAMF_OUT_TL_IDR_ns, MPAMF_OUT_TL_IDR_rt, or MPAMF_OUT_TL_IDR_rl.
MPAMF_OUT_TL_IDR_ns is permitted to have either the same or different contents to MPAMF_OUT_TL_IDR_rt or MPAMF_OUT_TL_IDR_rl.
MPAMF_OUT_TL_IDR_rt is permitted to have either the same or different contents to MPAMF_OUT_TL_IDR_rl.

There must be separate registers in the Secure (MPAMF_OUT_TL_IDR_s), Non-secure (MPAMF_OUT_TL_IDR_ns), Root (MPAMF_OUT_TL_IDR_rt), and Realm (MPAMF_OUT_TL_IDR_rl) MPAM feature pages.

MPAMF_OUT_TL_IDR can be accessed through the memory-mapped interfaces:

Component	Frame	Offset	Instance
MPAM	MPAMF_BASE_s	0x3200	MPAMF_OUT_TL_IDR_s

Accesses to this register are RO.

Component	Frame	Offset	Instance
MPAM	MPAMF_BASE_ns	0x3200	MPAMF_OUT_TL_IDR_ns

Accesses to this register are RO.

Component	Frame	Offset	Instance
MPAM	MPAMF_BASE_rt	0x3200	MPAMF_OUT_TL_IDR_rt

When FEAT_RME is implemented, accesses to this register are RO.

Component	Frame	Offset	Instance
MPAM	MPAMF_BASE_rl	0x3200	MPAMF_OUT_TL_IDR_rl

When FEAT_RME is implemented, accesses to this register are RO.

15/12/2024 22:27; 5e0a212688c6bd7aee92394b6f5e491b4d0fee1d

MPAMF_OUT_TL_IDR, MPAM Egress PARTID Translation ID Register

Purpose

Configuration

Attributes

Field descriptions

HAS_DIRECT_TL, bit [31]

HAS_BASE_MASK, bit [30]

Bits [29:16]

OUT_PARTID_MAX, bits [15:0]When MPAMF_OUT_TL_IDR.HAS_DIRECT_TL == 1:

Otherwise:

Accessing MPAMF_OUT_TL_IDR

MPAMF_OUT_TL_IDR can be accessed through the memory-mapped interfaces:

OUT_PARTID_MAX, bits [15:0]
When MPAMF_OUT_TL_IDR.HAS_DIRECT_TL == 1: