The TRCPIDR1 characteristics are:
Provides discovery information about the component.
For additional information, see the CoreSight Architecture Specification.
This register is present only when FEAT_ETE is implemented and FEAT_TRC_EXT is implemented. Otherwise, direct accesses to TRCPIDR1 are RES0.
TRCPIDR1 is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | DES_0 | PART_1 |
Reserved, RES0.
Designer, JEP106 identification code, bits [3:0].
JEP106 identification and continuation codes, which are stored as follows:
These codes indicate the designer of the component and not the implementer, except where the two are the same. To obtain a number, or to see the assignment of these codes, contact JEDEC http://www.jedec.org.
A JEDEC code takes the following form:
The parity bit in the JEP106 identification code is not included.
For example, Arm Limited is assigned the code 0x7F 0x7F 0x7F 0x7F 0x3B.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Part number, bits [11:8].
The part number is selected by the designer of the component, and is stored in TRCPIDR1.PART_1 and TRCPIDR0.PART_0.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
External debugger accesses to this register are unaffected by the OS Lock.
Component | Offset | Instance |
---|---|---|
ETE | 0xFE4 | TRCPIDR1 |
Accessible as follows:
15/12/2024 22:27; 5e0a212688c6bd7aee92394b6f5e491b4d0fee1d
Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.