Add horizontally vector elements to ZA tile
Add each element of the source vector to the corresponding active element of each horizontal slice of a ZA tile. The tile elements are predicated by a pair of predicates. An element of a horizontal slice is considered active if the corresponding second source predicate element is TRUE and the first source predicate element corresponding to the horizontal slice number is also TRUE. Inactive elements in the destination tile remain unmodified.
ID_AA64SMFR0_EL1.I16I64 indicates whether the 64-bit integer variant is implemented.
It has encodings from 2 classes: 32-bit and 64-bit
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | Pm | Pn | Zn | 0 | 0 | 0 | ZAda | |||||||||
| V | |||||||||||||||||||||||||||||||
if !HaveSME() then UNDEFINED; integer esize = 32; integer a = UInt(Pn); integer b = UInt(Pm); integer n = UInt(Zn); integer da = UInt(ZAda);
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | Pm | Pn | Zn | 0 | 0 | ZAda | ||||||||||
| V | |||||||||||||||||||||||||||||||
if !HaveSMEI16I64() then UNDEFINED; integer esize = 64; integer a = UInt(Pn); integer b = UInt(Pm); integer n = UInt(Zn); integer da = UInt(ZAda);
| <ZAda> |
For the 32-bit variant: is the name of the ZA tile ZA0-ZA3, encoded in the "ZAda" field. |
|
For the 64-bit variant: is the name of the ZA tile ZA0-ZA7, encoded in the "ZAda" field. |
| <Pn> |
Is the name of the first source scalable predicate register P0-P7, encoded in the "Pn" field. |
| <Pm> |
Is the name of the second source scalable predicate register P0-P7, encoded in the "Pm" field. |
| <Zn> |
Is the name of the source scalable vector register, encoded in the "Zn" field. |
CheckStreamingSVEAndZAEnabled(); integer dim = VL DIV esize; bits(PL) mask1 = P[a]; bits(PL) mask2 = P[b]; bits(VL) operand_src = Z[n]; bits(dim*dim*esize) operand_acc = ZAtile[da, esize]; bits(dim*dim*esize) result; for col = 0 to dim-1 bits(esize) element = Elem[operand_src, col, esize]; for row = 0 to dim-1 bits(esize) res = Elem[operand_acc, row*dim+col, esize]; if ElemP[mask1, row, esize] == '1' && ElemP[mask2, col, esize] == '1' then res = res + element; Elem[result, row*dim+col, esize] = res; ZAtile[da, esize] = result;
If FEAT_SVE2 is enabled or FEAT_SME is enabled, then when PSTATE.DIT is 1:
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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