Compute vector address
Optionally sign or zero-extend the least significant 32-bits of each element from a vector of offsets or indices in the second source vector, scale each index by 2, 4 or 8, add to a vector of base addresses from the first source vector, and place the resulting addresses in the destination vector. This instruction is unpredicated.
It has encodings from 3 classes: Packed offsets , Unpacked 32-bit signed offsets and Unpacked 32-bit unsigned offsets
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | sz | 1 | Zm | 1 | 0 | 1 | 0 | msz | Zn | Zd | |||||||||||||
if !HaveSVE() then UNDEFINED; integer esize = 32 << UInt(sz); integer n = UInt(Zn); integer m = UInt(Zm); integer d = UInt(Zd); integer osize = esize; boolean unsigned = TRUE; integer mbytes = 1 << UInt(msz);
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | Zm | 1 | 0 | 1 | 0 | msz | Zn | Zd | |||||||||||||
if !HaveSVE() then UNDEFINED; integer esize = 64; integer n = UInt(Zn); integer m = UInt(Zm); integer d = UInt(Zd); integer osize = 32; boolean unsigned = FALSE; integer mbytes = 1 << UInt(msz);
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | Zm | 1 | 0 | 1 | 0 | msz | Zn | Zd | |||||||||||||
if !HaveSVE() then UNDEFINED; integer esize = 64; integer n = UInt(Zn); integer m = UInt(Zm); integer d = UInt(Zd); integer osize = 32; boolean unsigned = TRUE; integer mbytes = 1 << UInt(msz);
| <Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
| <T> |
Is the size specifier,
encoded in
|
| <Zn> |
Is the name of the base scalable vector register, encoded in the "Zn" field. |
| <Zm> |
Is the name of the offset scalable vector register, encoded in the "Zm" field. |
| <mod> |
Is the index extend and shift specifier,
encoded in
|
| <amount> |
Is the index shift amount,
encoded in
|
CheckNonStreamingSVEEnabled(); integer elements = VL DIV esize; bits(VL) base = Z[n]; bits(VL) offs = Z[m]; bits(VL) result; for e = 0 to elements-1 bits(esize) addr = Elem[base, e, esize]; integer offset = Int(Elem[offs, e, esize]<osize-1:0>, unsigned); Elem[result, e, esize] = addr + (offset * mbytes); Z[d] = result;
If FEAT_SVE2 is enabled or FEAT_SME is enabled, then when PSTATE.DIT is 1:
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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