Bitwise AND (immediate), setting flags, performs a bitwise AND of a register value and an immediate value, and writes the result to the destination register. It updates the condition flags based on the result.
This instruction is used by the alias TST (immediate).
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| sf | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | N | immr | imms | Rn | Rd | ||||||||||||||||||
| opc | |||||||||||||||||||||||||||||||
integer d = UInt(Rd); integer n = UInt(Rn); integer datasize = if sf == '1' then 64 else 32; boolean setflags; LogicalOp op; case opc of when '00' op = LogicalOp_AND; setflags = FALSE; when '01' op = LogicalOp_ORR; setflags = FALSE; when '10' op = LogicalOp_EOR; setflags = FALSE; when '11' op = LogicalOp_AND; setflags = TRUE; bits(datasize) imm; if sf == '0' && N != '0' then UNDEFINED; (imm, -) = DecodeBitMasks(N, imms, immr, TRUE);
| <Wd> |
Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field. |
| <Wn> |
Is the 32-bit name of the general-purpose source register, encoded in the "Rn" field. |
| <Xd> |
Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field. |
| <Xn> |
Is the 64-bit name of the general-purpose source register, encoded in the "Rn" field. |
| <imm> |
For the 32-bit variant: is the bitmask immediate, encoded in "imms:immr". |
|
For the 64-bit variant: is the bitmask immediate, encoded in "N:imms:immr". |
| Alias | Is preferred when |
|---|---|
| TST (immediate) | Rd == '11111' |
bits(datasize) result; bits(datasize) operand1 = X[n]; bits(datasize) operand2 = imm; case op of when LogicalOp_AND result = operand1 AND operand2; when LogicalOp_ORR result = operand1 OR operand2; when LogicalOp_EOR result = operand1 EOR operand2; if setflags then PSTATE.<N,Z,C,V> = result<datasize-1>:IsZeroBit(result):'00'; if d == 31 && !setflags then SP[] = result; else X[d] = result;
If PSTATE.DIT is 1:
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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