Bit Clear and Exclusive OR performs a bitwise AND of the 128-bit vector in a source SIMD&FP register and the complement of the vector in another source SIMD&FP register, then performs a bitwise exclusive OR of the resulting vector and the vector in a third source SIMD&FP register, and writes the result to the destination SIMD&FP register.
This instruction is implemented only when FEAT_SHA3 is implemented.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | Rm | 0 | Ra | Rn | Rd | ||||||||||||||||
if !HaveSHA3Ext() then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); integer a = UInt(Ra);
| <Vd> |
Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
| <Vn> |
Is the name of the first SIMD&FP source register, encoded in the "Rn" field. |
| <Vm> |
Is the name of the second SIMD&FP source register, encoded in the "Rm" field. |
| <Va> |
Is the name of the third SIMD&FP source register, encoded in the "Ra" field. |
AArch64.CheckFPAdvSIMDEnabled(); bits(128) Vm = V[m]; bits(128) Vn = V[n]; bits(128) Va = V[a]; V[d] = Vn EOR (Vm AND NOT(Va));
If PSTATE.DIT is 1:
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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