Bitfield Clear sets a bitfield of <width> bits at bit position <lsb> of the destination register to zero, leaving the other destination bits unchanged.
This is an alias of BFM. This means:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| sf | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | N | immr | imms | 1 | 1 | 1 | 1 | 1 | Rd | ||||||||||||||
| opc | Rn | ||||||||||||||||||||||||||||||
is equivalent to
BFM <Wd>, WZR, #(-<lsb> MOD 32), #(<width>-1)
and is the preferred disassembly when UInt(imms) < UInt(immr).
is equivalent to
BFM <Xd>, XZR, #(-<lsb> MOD 64), #(<width>-1)
and is the preferred disassembly when UInt(imms) < UInt(immr).
| <Wd> |
Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field. |
| <Xd> |
Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field. |
| <width> |
For the 32-bit variant: is the width of the bitfield, in the range 1 to 32-<lsb>. |
|
For the 64-bit variant: is the width of the bitfield, in the range 1 to 64-<lsb>. |
The description of BFM gives the operational pseudocode for this instruction.
If PSTATE.DIT is 1:
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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