Break before first true condition
Sets destination predicate elements up to but not including the first active and true source element to true, then sets subsequent elements to false. Inactive elements in the destination predicate register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected. Does not set the condition flags.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | Pg | 0 | Pn | M | Pd | |||||||||
| B | S | ||||||||||||||||||||||||||||||
if !HaveSVE() && !HaveSME() then UNDEFINED; integer esize = 8; integer g = UInt(Pg); integer n = UInt(Pn); integer d = UInt(Pd); boolean merging = (M == '1'); boolean setflags = FALSE;
| <Pd> |
Is the name of the destination scalable predicate register, encoded in the "Pd" field. |
| <Pg> |
Is the name of the governing scalable predicate register, encoded in the "Pg" field. |
| <ZM> |
Is the predication qualifier,
encoded in
|
| <Pn> |
Is the name of the source scalable predicate register, encoded in the "Pn" field. |
CheckSVEEnabled(); integer elements = VL DIV esize; bits(PL) mask = P[g]; bits(PL) operand = P[n]; bits(PL) operand2 = P[d]; boolean break = FALSE; bits(PL) result; for e = 0 to elements-1 boolean element = ElemP[operand, e, esize] == '1'; if ElemP[mask, e, esize] == '1' then break = break || element; ElemP[result, e, esize] = if !break then '1' else '0'; elsif merging then ElemP[result, e, esize] = ElemP[operand2, e, esize]; else ElemP[result, e, esize] = '0'; if setflags then PSTATE.<N,Z,C,V> = PredTest(mask, result, esize); P[d] = result;
Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41
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