BSL

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

313029282726252423222120191817161514131211109876543210
0Q101110011Rm000111RnRd
opc2

BSL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); integer esize = 8; integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize; VBitOp op; case opc2 of when '00' op = VBitOp_VEOR; when '01' op = VBitOp_VBSL; when '10' op = VBitOp_VBIT; when '11' op = VBitOp_VBIF;

Assembler Symbols

<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T>

Is an arrangement specifier, encoded in Q:

Q <T>
0 8B
1 16B
<Vn>

Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Vm>

Is the name of the second SIMD&FP source register, encoded in the "Rm" field.

Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand1; bits(datasize) operand2; bits(datasize) operand3; bits(datasize) operand4 = V[n]; case op of when VBitOp_VEOR operand1 = V[m]; operand2 = Zeros(); operand3 = Ones(); when VBitOp_VBSL operand1 = V[m]; operand2 = operand1; operand3 = V[d]; when VBitOp_VBIT operand1 = V[d]; operand2 = operand1; operand3 = V[m]; when VBitOp_VBIF operand1 = V[d]; operand2 = operand1; operand3 = NOT(V[m]); V[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);

Operational information

If PSTATE.DIT is 1:


Internal version only: isa v33.11seprel, AdvSIMD v29.05, pseudocode v2021-09_rel, sve v2021-09_rc3d ; Build timestamp: 2021-10-06T11:41

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